Assembly line tight coupling accelerator interface structure based on instruction extension

Abstract

The invention discloses an assembly line tight coupling accelerator interface structure based on instruction extension, which comprises a correlation detection module and an acceleration engine; the correlation detection module is arranged at a decoding stage and is used for detecting data correlation of an acceleration instruction to register file RF access; after the acceleration instruction enters a decoding stage, a related detection module is started, a register file RF access request is input, and only when it is judged that correlation is generated, a blocking response signal is generated; the acceleration engine is arranged at the operation execution stage; the decoding stage activates an acceleration engine component through an accelerator access request signal sent by an inter-stage register reg3; at the moment, the operation execution component is in a bypass state, access responses of the operation execution component and the accelerator enter the multiplexer MUX1, and themultiplexer MUX1 selects a corresponding result under the action of an acceleration instruction identification signal and sends the result to the inter-stage register reg4. The assembly line tight coupling accelerator interface structure has extremely high universality and is suitable for most processor systems.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit design and processor design, and in particular relates to a pipeline tightly coupled accelerator interface structure based on instruction expansion. Background technique [0002] At present, VLSI represented by processors has always been a direction with the highest complexity and technical difficulty in the field of microelectronics, and its exploration and innovation in architecture has never stopped. The traditional microprocessor design is based on the standard ISA (Instruction Set Architecture), and completes the pipeline design of timing balance, in which the execution stage implements the logic, arithmetic and other instruction functions stipulated by the ISA. In general, the orthogonality of ISA can ensure that higher-level functional operations can be constructed based on basic operations. However, this basic instruction brings versatility and also brings performance problems t...

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Problems solved by technology

[0004] (1) A heterogeneous multi-core system is adopted. The main control processor is responsible for global program scheduling and control, while the coprocessor is responsible for image, video, codec and other intensive computing applications. The advantage of this system is that it can be quickly completed for special applications. Heterogeneous system design shortens the development cycle and design risk, but the disadvantage is that different processor cores may use different instruction sets, making software development difficult and poor portability;

[0005] (2) The "master-slave" IP integration form is adopted. Compared with the heterogeneous system, the coprocessor here has no instruction system, and only passively performs data processing according to the command of the main processor according to the established state machine, and the data processing The result is fed back to the main processor. The advantage of this system is that it eliminates the problem of instruction set compatibility, but the disadvantage is that the issuing and feedback of the main control command takes a long time, and the real-time performance of hardware acceleration is poor;

[0006] (3) The pipeline tight coupling structure is adopted, and blocking execution is adopted. When the floating-point acceleration instruction enters the pipeline, the accelerator takes over the execution of the instruction, and at the same time suspends the main pipeline. The advantage of this structure is that the acceleration instruction is at the speed of the main frequency of the system. Execution, instruction startup and result return have the highest real-time performance. On the one hand, this solution still parses fine-grained basic instructions, which only accelerate micro-operations, and the acceleration effect on complex applications is not good. At the same time, this solution often uses blocking Execute in the same way, which has a great influence on the execution of the main control program

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