A Pipeline Tightly Coupled Accelerator Interface Structure Based on Instruction Expansion

Abstract

The invention discloses a pipeline tightly coupled accelerator interface structure based on instruction expansion, which includes a correlation detection module and an acceleration engine. The correlation detection module is set at the decoding level and is used to detect the data correlation of the acceleration instruction to the RF access of the register file; when the acceleration After the instruction enters the decoding stage, start the relevant detection module, input the RF access request of the register file, and generate a blocking response signal only when it is judged that there is a correlation; the acceleration engine is set at the operation execution stage, and the decoding stage sends it through the interstage register reg3 The accelerator access request signal activates the acceleration engine part, and the operation execution part is in the bypass state at this time, and the access response between the operation execution part and the accelerator enters the multiplexer MUX1, and the multiplexer MUX1 will select the corresponding acceleration command identification signal. The result is sent to the interstage register reg4. The invention has extremely strong versatility and is suitable for most processor systems.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit design and processor design, and in particular relates to a pipeline tightly coupled accelerator interface structure based on instruction expansion. Background technique [0002] At present, VLSI represented by processors has always been a direction with the highest complexity and technical difficulty in the field of microelectronics, and its exploration and innovation in architecture has never stopped. The traditional microprocessor design is based on the standard ISA (Instruction Set Architecture), and completes the pipeline design of timing balance, in which the execution stage implements the logic, arithmetic and other instruction functions stipulated by the ISA. In general, the orthogonality of ISA can ensure that higher-level functional operations can be constructed based on basic operations. However, this basic instruction brings versatility and also brings performance problems t...

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Problems solved by technology

[0004] (1) A heterogeneous multi-core system is adopted. The main control processor is responsible for global program scheduling and control, while the coprocessor is responsible for image, video, codec and other intensive computing applications. The advantage of this system is that it can be quickly completed for special applications. Heterogeneous system design shortens the development cycle and design risk, but the disadvantage is that different processor cores may use different instruction sets, making software development difficult and poor portability;

[0005] (2) The "master-slave" IP integration form is adopted. Compared with the heterogeneous system, the coprocessor here has no instruction system, and only passively performs data processing according to the command of the main processor according to the established state machine, and the data processing The result is fed back to the main processor. The advantage of this system is that it eliminates the problem of instruction set compatibility, but the disadvantage is that the issuing and feedback of the main control command takes a long time, and the real-time performance of hardware acceleration is poor;

[0006] (3) The pipeline tight coupling structure is adopted, and blocking execution is adopted. When the floating-point acceleration instruction enters the pipeline, the accelerator takes over the execution of the instruction, and at the same time suspends the main pipeline. The advantage of this structure is that the acceleration instruction is at the speed of the main frequency of the system. Execution, instruction startup and result return have the highest real-time performance. On the one hand, this solution still parses fine-grained basic instructions, which only accelerate micro-operations, and the acceleration effect on complex applications is not good. At the same time, this solution often uses blocking Execute in the same way, which has a great influence on the execution of the main control program

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