Time-to-digital convertoer and all-digital phase locked loop

Abstract

A time-to-digital converter (TDC) includes a converter which receives a first signal and a second signal, delays the second signal in phases using a plurality of delay elements which are coupled in series, compares the delayed second signal with the first signal, and outputs a phase error of the second signal with respect to the first signal, a phase frequency detector which receives the first signal, and a third signal from one of the nodes in the plurality of delay elements, and outputs a phase difference between the first signal and the third signal, and a frequency detector which outputs a frequency error of the second signal with respect to the first signal as a digital code using an output signal of the phase frequency detector and the second signal.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2009-0076780 filed with the Korean Intellectual Property Office on August 19, 2009 and U.S. Serial No. 61 / 118,693 filed to the United States Patent and Trademark Office on December 1, 2008 Priority of the patent, the disclosure of which is hereby incorporated by reference in its entirety. technical field [0002] Apparatus and methods consistent with the present invention relate to a time-to-digital converter (TDC) and an all-digital phase-locked loop (ADPLL) using the same, and more particularly, to a method capable of not only detecting the difference between two input signals Phase difference, digital-to-time converter that can also detect frequency difference and full digital phase-locked loop using it. Background technique [0003] With the development of technology, in advanced processing technology, all-digital phase-locked loop (ADPLL) is developed as a substitute of charge-pump phase-locked ...

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Problems solved by technology

However, the phase alignment accuracy of the relay type PFD is poor

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