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Low dropout linear regulator and pole adjustment method thereof

A technology of low-dropout linearity and voltage regulators, which is applied in the direction of instruments, electrical variable adjustment, control/regulation systems, etc. It can solve the problems of not being able to connect large capacitors to the output of LDOs, achieve low power consumption, ensure stability, and regulate The effect of small current

Active Publication Date: 2013-02-27
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] However, the development trend of LDO is more and more inclined to cancel the pin of the LDO output terminal. If there is no pin of the LDO output terminal, it is impossible to connect the large capacitor in the above method to the LDO output terminal off-chip. The problem of LDO frequency stability is will still exist

Method used

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  • Low dropout linear regulator and pole adjustment method thereof
  • Low dropout linear regulator and pole adjustment method thereof
  • Low dropout linear regulator and pole adjustment method thereof

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Embodiment Construction

[0029] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. In the following paragraphs, the present invention is described in more detail by way of example with reference to the drawings. According to the following description, the advantages and features of the present invention will become clearer.

[0030] Such as figure 2 As shown, the first embodiment of the present invention provides a low dropout linear regulator, including: an error amplifier OP, a first current supply unit 11, a second current supply unit 12, a PMOS adjustment transistor MP1, a first resistor R1, and a second Resistance R2.

[0031] The source of the PMOS adjusting transistor MP1 is connected to the first voltage terminal VDD, the drain is connected to the first end of the first resistor R1, and the gate is connected to the output terminal OUT1 of the error amplifier OP;

[0032] The first current supply unit 11 is adapted to gen...

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PUM

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Abstract

Disclosed are a low dropout linear regulator and a pole adjustment method thereof. A source electrode of a p-channel metal oxide semiconductor (PMOS) adjustment transistor of the low dropout linear regulator is connected with a first voltage end, a drain electrode of the PMOS adjustment transistor is connected with a first end of a first resistor, a grid electrode of the PMOS adjustment transistor is connected with an output end of an error amplifier, a first electric current supply unit is suitable for generating reference current, a second electric current supply unit is suitable for generating regulating current, the regulating current is relevant to the electric current of an output end of the low dropout linear regulator, a first input end of the error amplifier inputs reference voltage, a second input end of the error amplifier is connected with a second end of the first resistor and a first end of a second resistor, a bias current input end inputs bias current generated by superposition of the reference current and the regulating current, the first end of the first resistor serves as the output end of the low dropout linear regulator, a second end of the second resistor is connected with a second voltage end, and the voltage value of the first voltage end is larger than that of the second voltage end.

Description

Technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a low-dropout linear regulator and a pole adjustment method thereof. Background technique [0002] Low Dropout Regulator (LDO) is a step-down DC linear regulator. With the development of SOC technology, it has nowhere to be applied in industries such as computers, communications, instrumentation, consumer electronics, and camera monitoring. Not here. Although compared with DC-DC switching voltage converters, LDO has lower efficiency, but it has the advantages of fewer external components, small ripple, low noise, small chip area, simple circuit structure, etc., so LDO is used in power management chips Has always held a large proportion. [0003] With the improvement of integration, more and more LDOs are used as submodules of SOC (System on Chip) chips to supply power to a key module and integrated into the SOC chip, while the powerful SOC chip is integrated It is common ...

Claims

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Application Information

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IPC IPC(8): G05F1/56
Inventor 张志军
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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