Two-phase DC-DC topological structure with current multiplier

Abstract

The invention belongs to the technical field of power management, and particularly relates to a double-phase DC-DC topological structure with a current multiplier. The invention is characterized in that a current multiplier and a switched capacitor SC buck are embedded on the basis of the traditional multiphase buck, the inductive current and the RMS current of a buck power device are greatly reduced, the current stress is transferred to a charge pump structure of a low-voltage and low-FoM-value device, and the voltage stress is retained in a high-voltage device of the buck. And high conversion efficiency is realized through a strategy that the charge pump and the buck share current and voltage stress respectively. Meanwhile, due to the fact that the switched capacitor has extremely low output impedance, and the circuit is compatible with a loop control strategy of a traditional multi-phase buck, the transient response speed is also remarkably improved. The idea of the invention can be linearly expanded from typical two-phase buck to N-phase buck, so that the topological structure of the invention has universality.

Description

Technical Field

[0001] The present invention belongs to the technical field of power management, and particularly relates to a dual-phase DC-DC topology structure with a current multiplier. Background Art

[0002] With the development of the mobile Internet and the evolution of the artificial intelligence wave, the performance indicators and energy consumption of high-performance computing power chips CPU / GPU have been continuously improved. The requirements for the conversion efficiency, power density, transient characteristics, output ripple, etc. of the power supply system have also been continuously increased. In the application scenario of the three-stage power bus, the traditional solution adopts Figure 1 the multi-phase buck converter architecture shown in the figure. This solution is difficult to balance the future development trends of high frequency (5 MHz), miniaturization, and vertical power supply. Therefore, it is urgent to conduct innovative research from two aspects: power supply topology and circuit control.

[0003] The industry has also proposed many innovative solutions for PoL applications. Figure 2 The Sigma converter architecture is a representative one. In the figure, through the series connection of the input stage and the parallel connection of the output stage, the input voltage stress is shared among the high-voltage small-current and low-voltage small-current modules; the output current stress is distributed to the low-voltage large-current part operating in open loop and the small-current part operating in closed loop. Since the voltage and current stresses on the devices are reduced simultaneously, the overall efficiency is significantly improved. However, in the case of a wide dynamic input scenario, the power conversion ratio of the two parts cannot be controlled, and it is very easy to occur that the low-voltage small-current module processes high power, reducing the overall conversion efficiency. Summary of the Invention

[0004] In view of the above problems, the present invention mainly realizes a topology structure suitable for high-current and fast transient response scenarios.

[0005] To achieve the above object, the technical solution of the present invention is as follows:

[0006] A dual-phase DC-DC topology structure with a current multiplier, including a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, a sixth switch S6, a seventh switch S7, an eighth switch S8, a ninth switch S c1 , a tenth switch S c2 , an eleventh switch S c3 , a twelfth switch S c4 , a thirteenth switch S c5 , a fourteenth switch S c6 , a fifteenth switch S c7 , a sixteenth switch S c8 , a first capacitor C F1 , a second capacitor C F2 , a third capacitor C F3, the fourth capacitor C F4 , the first inductor L1, the second inductor L2; where:

[0007] The first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 are the power switch devices of the first-phase SC-buck. The input voltage is grounded after passing through the series-connected first switch S1, second switch S2, third switch S3, and fourth switch S4 in sequence. The two ends of the first capacitor C F1 are respectively connected to the connection point between the first switch S1 and the second switch S2 and the connection point between the third switch S3 and the fourth switch S4;

[0008] The fifth switch S5, the sixth switch S6, the seventh switch S7, and the eighth switch S8 are the power switch devices of the second-phase SC-buck. The input voltage is grounded after passing through the series-connected fifth switch S5, sixth switch S6, seventh switch S7, and eighth switch S8 in sequence. The two ends of the second capacitor C F2 are respectively connected to the connection point between the fifth switch S5 and the sixth switch S6 and the connection point between the seventh switch S7 and the eighth switch S8;

[0009] The ninth switch S c1 , the tenth switch S c2 , the eleventh switch S c3 , the twelfth switch S c4 , the thirteenth switch S c5 , the fourteenth switch S c6 , the fifteenth switch S c7 , the sixteenth switch S c8 , the third capacitor C F3 , the fourth capacitor C F4 constitute a current multiplier. The connection point between the second switch S2 and the third switch S3 is connected to the input end of the current multiplier through the first inductor L1; the input end of the current multiplier passes through the series-connected ninth switch S c1 , the tenth switch S c2 , the eleventh switch S c3 , the twelfth switch S c4 and then is grounded. The two ends of the fourth capacitor C F4 are respectively connected to the connection point between the ninth switch S c1 and the tenth switch S c2 and the connection point between the eleventh switch S c3 and the twelfth switch S c4 ; the input end of the current multiplier also passes through the series-connected thirteenth switch S c5 , the fourteenth switch S c6 , the fifteenth switch S c7 , the sixteenth switch S c8 and then is grounded. The two ends of the third capacitor C F3 are respectively connected to the thirteenth switch Sc5 Connected to the fourteenth switch S c6 The connection point and the fifteenth switch S c7 Connected to the sixteenth switch S c8 The connection point; the tenth switch S c2 Connected to the eleventh switch S c3 The connection point and the fourteenth switch S c6 Connected to the fifteenth switch S c7 After being connected, it serves as the output terminal of the current multiplier;

[0010] The connection point between the sixth switch S6 and the seventh switch S7 is connected to the output terminal of the current multiplier after passing through the second inductor L2, serving as the output terminal of the bi-phase DC-DC topology.

[0011] Furthermore, the bi-phase DC-DC includes ten working states, namely:

[0012] The first working state: S3, S4, S7, S8, S c1 , S c3 , S c6 , S c8 The switching tubes are closed, and the rest of the switching tubes are open;

[0013] The second working state: S1, S3, S7, S8, S c1 , S c3 , S c6 , S c8 The switching tubes are closed, and the rest of the switching tubes are open;

[0014] The third working state: S3, S4, S5, S7, S c1 , S c3 , S c6 , S c8 The switching tubes are closed, and the rest of the switching tubes are open;

[0015] The fourth working state: S2, S4, S7, S8, S c1 , S c3 , S c6 , S c8 The switching tubes are closed, and the rest of the switching tubes are open;

[0016] The fifth working state: S3, S4, S6, S8, S c1 , S c3 , S c6 , S c8 The switching tubes are closed, and the rest of the switching tubes are open;

[0017] In the above five states, the flying capacitors C F1 and C F2 have completed one round of charge and discharge energy cycle, but the flying capacitor C of the subsequent charge pumpF3 and C F4 are in the charging and discharging processes respectively. Therefore, the energy cycle in the second half period needs to charge and discharge C F3 and C F4 respectively.

[0018] Sixth working state: S3, S4, S7, S8, S c2 , S c4 , S c5 , S c7 switch tubes are closed, and the rest are open;

[0019] Seventh working state: S1, S3, S7, S8, S c2 , S c4 , S c5 , S c7 switch tubes are closed, and the rest are open;

[0020] Eighth working state: S3, S4, S5, S7, S c2 , S c4 , S c5 , S c7 switch tubes are closed, and the rest are open;

[0021] Ninth working state: S2, S4, S7, S8, S c2 , S c4 , S c5 , S c7 switch tubes are closed, and the rest are open;

[0022] Tenth working state: S3, S4, S6, S8, S c2 , S c4 , S c5 , S c7 switch tubes are closed, and the rest are open;

[0023] Among them, state one and state six represent the double-inductor freewheeling state.

[0024] Based on the ten working states, the timing of one working cycle is: the first working state, the second working state, the first working state, the third working state, the first working state, the fourth working state, the first working state, the fifth working state, the sixth working state, the seventh working state, the sixth working state, the eighth working state, the sixth working state, the ninth working state, the tenth working state.

[0025] Based on the above-mentioned dual-phase DC-DC topology, it can be extended to a multi-phase DC-DC topology. Specifically, the second-phase SC-buck is extended to be composed of multiple parallel SC-bucks. That is, in multiple-phase SC-bucks, after the first-phase SC-buck is connected in series with a current multiplier, it is then connected in parallel with other-phase SC-bucks.

[0026] The beneficial effects of the present invention are as follows: It supports a wide dynamic input-output scenario. Different from most innovative topologies limited by flying capacitors and having a conversion ratio not greater than 0.5, in the scenario of a large duty cycle (Duty>0.5), the power stage can degrade into the working mode of a standard three-level buck; the power distribution of two phases is controlled under wide dynamic changes, that is, the current-mode control architecture can limit the average power of each path, avoiding the situation of power mismatch between two phases in the sigma structure; the inductor current stress is significantly reduced. Description of the Drawings

[0027] Figure 1 is a traditional buck-type multi-phase DC-DC converter;

[0028] Figure 2 is a traditional sigma-type DC-DC converter;

[0029] Figure 3 is the conceptual diagram of the two-phase buck with a current multiplier of the present invention;

[0030] Figure 4 is the loop control model of the two-phase buck with a current multiplier of the present invention;

[0031] Figure 5 is the specific circuit diagram of the two-phase buck with a current multiplier of the present invention;

[0032] Figure 6 is the schematic diagram of the first working state;

[0033] Figure 7 is the schematic diagram of the second working state;

[0034] Figure 8 is the schematic diagram of the third working state;

[0035] Figure 9 is the schematic diagram of the fourth working state;

[0036] Figure 10 is the schematic diagram of the fifth working state;

[0037] Figure 11 is the schematic diagram of the sixth working state;

[0038] Figure 12 is the schematic diagram of the seventh working state;

[0039] Figure 13 It is a schematic diagram of the eighth working state;

[0040] Figure 14 It is a schematic diagram of the ninth working state;

[0041] Figure 15 It is a schematic diagram of the tenth working state;

[0042] Figure 16 It is the two-phase buck mode cycle diagram of the present invention with a current multiplier;

[0043] Figure 17 It is the multiphase buck topology diagram of the present invention with a current multiplier;

[0044] Figure 18 It is the inductor current and switch characteristic diagram of the two-phase buck of the present invention;

[0045] Figure 19 It is the transient jump waveform diagram of the two-phase buck load of the present invention;

[0046] Figure 20 It is the comparison diagram of the transient jump waveforms between the two-phase buck of the present invention and the traditional buck. Detailed implementation manners

[0047] The technical solution of the present invention will be analyzed and described in detail below with reference to the accompanying drawings.

[0048] The basic idea of the present invention is as Figure 3 shown. The present invention expects to embed a low-voltage and high-current unit as a current multiplier on the basis of the traditional two-phase buck, so as to proportionally reduce Figure 3 the current stress of the inductor L1 in, and the other converter adjusts the output in a closed loop to reduce the output ripple.

[0049] The loop control model of the present invention is as Figure 4 shown, including S1, S2, S3, S4, S5, S6, S7, S8, S c1 , S c2 , S c3 , S c4 , S c5 , S c6 , S c7 , S c8 , C F1 , C F2 , C F3 , C F4 , L1, and L2 are composed. Among them, S1-S8 are the power switch devices of the two-phase SC buck unit, and S c1 -S c8 are the power switch devices of the switched-capacitor type current multiplier, and CF1 and C F2 is the flying capacitor of the SC buck, C F3 and C F4 is the flying capacitor of the current multiplier. Finally, L1 and L2 are the output inductors of the SC buck. To simultaneously satisfy the charge and discharge balance relationship between the capacitor array of the SC buck and the interleaved charge pump, a large energy cycle period can be divided into ten states, as Figures 6 to 15 shown.

[0050] In Figure 6 state 1, C F1 and C F2 do not charge or discharge externally, and the inductors L1 and L2 maintain the freewheeling state. The freewheeling diodes S3, S4, S7, and S8 of the two-way SC buck are closed. The C F3 of the charge pump discharges externally, and C F4 is charged by V MID . Therefore, only S c1 , S c3 , S c6 , S c8 are closed. The architecture of the two-way interleaved charge pump adopted in the present invention can omit the intermediate bus capacitor of V MID . And the switching frequency is set to half of the SC buck frequency, and the output voltage ripple is reduced by increasing the capacitance values of C F3 and C F4 .

[0051] After entering Figure 7 state 2, the C F1 of the SC buck starts to enter the charging stage, and C F2 does not charge or discharge. The switching action of the charge pump remains unchanged.

[0052] After entering Figure 8 state 3, the C F2 of the SC buck starts to enter the charging stage, C F1 does not enter the charge and discharge cycle, and L1 discharges externally. The switching action of the charge pump remains unchanged.

[0053] After entering Figure 9 state 4, the C F1 of the SC buck starts to enter the discharging stage, C F2 does not enter the charge and discharge cycle, and L2 discharges externally. The switching action of the charge pump remains unchanged.

[0054] After entering Figure 10 state 5, the C F2 of the SC buck starts to enter the discharging stage, C F1 does not enter the charge and discharge cycle, and L1 discharges externally. The switching action of the charge pump remains unchanged.

[0055] Figure 11 The difference between state 6 and state 1 lies in the flying capacitor C of the charge pump F3 and C F4 starting to exchange the charge and discharge timing sequence. Since the flying capacitors of the charge pump in states 1 - 5 remain unchanged and are always in the state of C F3 discharging and C F4 charging. Therefore, state 6 switches the state of the charge pump, that is, S c2 、S c4 、S c5 、S c7 are closed, realizing that C F3 is charged by V MID and C F4 discharges to the output.

[0056] The C of the SC buck F2 starts to enter the discharge stage, C F1 does not enter the charge and discharge cycle and L1 freewheels externally, and the charge pump switch action remains unchanged. Therefore, during the period from state 7 to state 10, for the SC buck, it is the same as that from state 2 to state 5, and the charge and discharge cycles of C F1 and C F2 are completed

[0057] Figure 16 shows the timing diagram of the entire system completing one working cycle. The diagram is divided into two loop circles. The left represents the charge pump C F3 discharging and C F4 charging cycle, and the right represents the C F3 charging and C F4 discharging cycle. The two-phase interleaved charge pumps of the present invention are connected in parallel to form a current multiplier unit. C F1 and C F2 are equivalent to series capacitors under the voltage of V MID , and the capacitor voltages of the two will always be maintained at V MID / 2, and dynamic balance can be maintained.

[0058] In summary, after ten states, the system completes the energy cycle of charge and discharge, and the inductor current also reaches volt - second balance. Since the charge pump is a 2:1 step - down voltage pump, therefore V MID = 2 * V out , and the volt - second balance formulas for inductors L1 and L2 can be given as follows:

[0059]

[0060] On the other hand, Figure 5 the average currents of L1 and L2 in MIDWhile increasing the voltage, the average current of i is doubled. L1 The average current of the multi-phase buck is simultaneously controlled by the current-mode loop, and the average currents of L1 and L2 are equal. From this, the mathematical relationship between i L1 and i L2 can be obtained:

[0061]

[0062] According to formula (3), when the number of buck phases k in the current multiplier branch is larger, the average inductor current will be further reduced. When the two-phase buck of the current multiplier of the present invention is extended to Figure 17 the N-phase buck shown, the mathematical relationship between the inductor current and the output current of each path is shown in formula (4):

[0063]

[0064] It can be seen from formula (4) that the current multiplier technology adopted by the present invention can greatly reduce the current stress of the inductor and the buck power device, and transfer this part of the stress to the current multiplier of the low-voltage and low FoM value devices. The design goal of high-voltage devices dealing with high-voltage small currents and low-voltage devices dealing with low-voltage large currents is achieved, and the conversion efficiency is greatly improved.

[0065] In terms of loop control, the present invention is compatible with the traditional multi-phase buck control scheme. Figure 4 The current-mode control strategy shown directly samples the ripple currents of L1 and L2 as ripple injection, and the voltage outer loop directly samples the final output voltage V out as the feedback point, without monitoring and controlling the input voltage V MID of the current multiplier. This approach is consistent with the traditional two-phase buck and has good compatibility.

[0066] The simulation waveform of the working principle of the two-phase buck with a current multiplier of the present invention is as shown in Figure 18 . The input voltage is 24V and the output voltage is 1.2V. Figure 6 In it, V sw1 and i L1 refer to the switch node and inductor current waveforms of the current multiplier SC buck. V sw2 and i L2 are the corresponding waveforms of the other small-duty-cycle SC buck. Figure 18 It can be seen in that the peak values of the inductor currents of the two paths are limited by the current limit of EA, so the average currents of the two are not very different, and the difference in the ripple current comes from the current multiplier composed of the charge pump. The two-phase buck maintains a working timing of 180° staggered turn-on.

[0067] The dual-phase buck transient characteristics of the current multiplier proposed by the present invention are as follows Figure 19 and Figure 20 shown. In this simulation bench, the input voltage is maintained at 24V, the output voltage is 1.2V, the output capacitance is 44uF, the inductances L1 and L2 are both 1uH, and the switching frequency is 2MHz. Figure 19 shows the variation characteristics of the output voltage and V MID voltage when the topology of the present invention jumps from light load to heavy load. When the load changes from 0.5 - 12A@12ns, the output voltage drops by 80mV, and V MID this intermediate bus voltage also rapidly increases by 100mV to provide a stable V out . Figure 19 On the right is the operating condition of the topology of the present invention when jumping from heavy load to light load. Among them, the output voltage also overshoots by about 80mV, and V MID voltage rapidly decreases by 100mV to adapt to the new DC operating point.

[0068] Figure 20 The dotted line in Figure 20 represents the transient characteristic curve of the traditional dual-phase buck, and the solid line in Figure 20 represents the transient characteristic curve of the dual-phase buck with a current multiplier proposed by the present invention. The transient characteristics are compared under exactly the same operating conditions. Among them Figure 20 the left side represents the operating condition of jumping from light load to heavy load. The output voltage drop of the present invention is about 80mV, and the output voltage drop of the traditional scheme is 120mV. Therefore, the voltage drop Vus of the present invention's scheme is reduced by 33% compared to the traditional scheme. And out it can also be clearly seen from the inductor current shown that the average value of the inductor current of the present invention is also lower than that of the traditional scheme. The average inductor current of the two-phase buck in the traditional scheme is 1 / 2I

[0069] Figure 20 out, that is, 6A. While the current multiplier of the present invention reduces the inductor current to 1 / 3Iout, that is, 4A.

[0070] The features of the present invention are that a current multiplier and a switched-capacitor (SC) buck are embedded on the basis of a traditional multiphase buck, achieving a significant reduction in the inductor current and the RMS current of the buck power device, transferring the current stress to the charge pump structure of low-voltage and low FoM-value devices, and retaining the voltage stress in the high-voltage devices of the buck. Through the strategy of the charge pump and the buck sharing the current and voltage stresses respectively, high conversion efficiency is achieved. At the same time, thanks to the extremely low output impedance of the switched capacitor and the compatibility of the present invention with the loop control strategy of the traditional multiphase buck, the transient response speed is also significantly improved. The idea of the present invention can be linearly extended from a typical two-phase buck to an N-phase buck. Thus, it can be seen that the topology of the present invention has universality.

Claims

1. A dual-phase DC-DC topology with a current multiplier, characterized in that, Including a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, a sixth switch S6, a seventh switch S7, an eighth switch S8, a ninth switch S c1 , a tenth switch S c2 , an eleventh switch S c3 , a twelfth switch S c4 , a thirteenth switch S c5 , a fourteenth switch S c6 , a fifteenth switch S c7 , a sixteenth switch S c8 , a first capacitor C F1 , a second capacitor C F2 , a third capacitor C F3 , a fourth capacitor C F4 , a first inductor L1, a second inductor L2; wherein: The first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 are the power switch devices of the first-phase SC-buck. The input voltage is grounded after passing through the series-connected first switch S1, second switch S2, third switch S3, and fourth switch S4 in sequence. The two ends of the first capacitor C F1 are respectively connected to the connection point between the first switch S1 and the second switch S2 and the connection point between the third switch S3 and the fourth switch S4; The fifth switch S5, the sixth switch S6, the seventh switch S7, and the eighth switch S8 are the power switch devices of the second-phase SC-buck. The input voltage is grounded after passing through the serially connected fifth switch S5, sixth switch S6, seventh switch S7, and eighth switch S8 in sequence. The two ends of the second capacitor C F2 are respectively connected to the connection point between the fifth switch S5 and the sixth switch S6 and the connection point between the seventh switch S7 and the eighth switch S8; The ninth switch S c1 and the tenth switch S c2 and the eleventh switch S c3 and the twelfth switch S c4 and the thirteenth switch S c5 and the fourteenth switch S c6 and the fifteenth switch S c7 and the sixteenth switch S c8 and the third capacitor C F3 and the fourth capacitor C F4 constitute a current multiplier. The connection point of the second switch S2 and the third switch S3 is connected to the input end of the current multiplier through the first inductor L1; the input end of the current multiplier passes through the ninth switch S c1 and the tenth switch S c2 and the eleventh switch S c3 and the twelfth switch S c4 in series and then grounded. The two ends of the fourth capacitor C F4 are respectively connected to the connection point of the ninth switch S c1 and the tenth switch S c2 and the connection point of the eleventh switch S c3 and the twelfth switch S c4 ; the input end of the current multiplier also passes through the thirteenth switch S c5 and the fourteenth switch S c6 and the fifteenth switch S c7 and the sixteenth switch S c8 in series and then grounded. The two ends of the third capacitor C F3 are respectively connected to the connection point of the thirteenth switch S c5 and the fourteenth switch S c6 and the connection point of the fifteenth switch S c7 and the sixteenth switch S c8 ; the connection point of the tenth switch S c2 and the eleventh switch S c3 and the connection point of the fourteenth switch S c6 and the fifteenth switch S c7 are connected and used as the output end of the current multiplier; The connection point of the sixth switch S6 and the seventh switch S7 is connected to the output end of the current multiplier after passing through the second inductor L2, serving as the output end of the dual-phase DC-DC topology.

2. A two-phase DC-DC topology with a current multiplier according to claim 1, characterized in that, The dual-phase DC-DC includes ten operating states, namely: First working state: S3, S4, S7, S8, S c1 , S c3 , S c6 , S c8 switches are closed and the rest are open; Second working state: S1, S3, S7, S8, S c1 , S c3 , S c6 , S c8 switches are closed, and the rest of the switches are open; Third working state: S3, S4, S5, S7, S c1 , S c3 , S c6 , S c8 The switch is closed and the rest of the switches are open; Fourth working state: S2, S4, S7, S8, S c1 , S c3 , S c6 , S c8 The switch is closed and the rest of the switches are open; Fifth working state: S3, S4, S6, S8, S c1 , S c3 , S c6 , S c8 The switch is closed and the rest of the switches are open; Sixth working state: S3, S4, S7, S8, S c2 , S c4 , S c5 , S c7 The switch is closed and the rest of the switches are open; The seventh working state: S1, S3, S7, S8, S c2 , S c4 , S c5 , S c7 switches are closed and the rest of the switches are open; Eighth operating state: S3, S4, S5, S7, S c2 , S c4 , S c5 , S c7 switches are closed and the rest are open; Ninth working state: S2, S4, S7, S8, S c2 , S c4 , S c5 , S c7 The switch is closed and the rest of the switches are open; Tenth working state: S3, S4, S6, S8, S c2 , S c4 , S c5 , S c7 The switch is closed and the rest of the switches are open; Based on the ten operating states, the timing of one operating cycle is: the first operating state, the second operating state, the first operating state, the third operating state, the first operating state, the fourth operating state, the first operating state, the fifth operating state, the sixth operating state, the seventh operating state, the sixth operating state, the eighth operating state, the sixth operating state, the ninth operating state, the tenth operating state.

3. A multiphase DC-DC topology with a current multiplier, based on the dual-phase DC-DC topology with a current multiplier described in claim 1, characterized in that, The second-phase SC-buck is extended and formed by multiple phases of SC-buck connected in parallel.

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