Semiconductor device provided with vertical semiconductor element

A semiconductor and device technology, applied in the field of semiconductor devices including vertical semiconductor elements

Inactive Publication Date: 2014-05-28
DENSO CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, in case the voltage drop in the extraction path is too large, the avalanche current flows towards n + type source region flow to operate parasitic bipolar transistor

Method used

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  • Semiconductor device provided with vertical semiconductor element
  • Semiconductor device provided with vertical semiconductor element
  • Semiconductor device provided with vertical semiconductor element

Examples

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no. 1 example ）

[0033] A first embodiment of the present disclosure will be described. In this embodiment, a semiconductor device including a vertical MOS transistor as a vertical semiconductor element will be described as an example. figure 1 is a cross-sectional view showing the cell region Rc of the semiconductor device including the vertical MOS transistor according to the present embodiment. figure 2 is showing figure 1 A diagram of the layout of the semiconductor device is shown. figure 1 corresponds to along figure 2 A cross-sectional view taken along line I-I in .

[0034] in accordance with figure 1 In the semiconductor device of the present embodiment shown, an inverted vertical MOS transistor having a trench gate structure is provided as the vertical MOS transistor. like figure 1 shown, using n + Type substrate 1 forms a vertical MOS transistor. in n + In the substrate 1, one surface is referred to as a main surface 1a, and the opposite surface is referred to as a rear s...

no. 2 example ）

[0055] A second embodiment of the present disclosure will be described. In this embodiment, the configuration of the super junction structure is changed from that of the first embodiment, while other parts are similar to the first embodiment. Therefore, only parts different from the first embodiment will be described.

[0056] Figure 6 is a cross-sectional view showing the cell region Rc of the semiconductor device including the vertical MOS transistor according to the present embodiment. Such as Figure 6 As shown, in this embodiment, a dummy gate structure is formed at the position where the n-type region 2b is formed. Specifically, the longitudinal directions of the first trench 7 and the second trench 10 are set to be the same direction as the longitudinal directions of the n-type region 2 b and the p-type region 3 . First trench 7 is arranged in every other n-type region 2b, and second trench 10 is formed at a portion of n-type region 2b where first trench 7 is not f...

no. 3 example ）

[0059] A third embodiment of the present disclosure will be described. In this embodiment, the configuration of the super junction structure is changed from that of the first embodiment, while other parts are similar to the first embodiment. Therefore, only parts different from the first embodiment will be described.

[0060] 7( a ) to 7( b ) are cross-sectional views showing the cell region Rc of the semiconductor device including the vertical MOS transistor according to the present embodiment. Figure 8 is a diagram showing the layout of the semiconductor device shown in FIG. 7 . Figure 7(a) and Figure 7(b) respectively correspond to the Figure 8 A cross-sectional view taken along lines VIIA-VIIA, VIIB-VIIB in .

[0061] Figure 7 (a), (b) and Figure 8 As shown, in this embodiment, the longitudinal direction of the first trench 7 and the second trench 10 is set to intersect the longitudinal direction of the n-type region 2b and the p-type region 3, so that the trench ga...

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Abstract

This semiconductor device that is provided with a vertical semiconductor element has a trench gate structure and a dummy gate structure. The trench gate structure has a first trench (7) which is formed to reach a first conductivity-type region (2b) in a super junction structure by penetrating a first impurity region (5) and a base region (4). The dummy gate structure has a second trench (10), which reaches the super junction structure by penetrating the base region (4), and is formed deeper than the first trench (7).

Description

[0001] Cross References to Related Applications [0002] This disclosure is based on Japanese Patent Application No. 2011-210676 filed on September 27, 2011 and Japanese Patent Application No. 2012-161523 filed on July 20, 2012, the disclosures of which are incorporated herein by reference . technical field [0003] The present disclosure relates to semiconductor devices including vertical semiconductor elements. Background technique [0004] In semiconductor devices including vertical MOS transistors, holes are usually extracted from the p-type base region. However, in case the voltage drop in the extraction path is too large, the avalanche current flows towards n + Type source region flow to operate the parasitic bipolar transistor. Therefore, the avalanche resistance is reduced. In order to improve the avalanche resistance, it is necessary not to operate by n + type source region, p-type base region and n - A parasitic bipolar transistor formed by a type drift layer...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78H01L21/336H01L29/06
CPCH01L29/407H01L29/1045H01L29/0634H01L29/78H01L29/41766H01L29/7813H01L29/06H01L29/1095H01L29/66734
Inventor 利田祐麻赤木望
Owner DENSO CORP
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