Process for electrodeposition of copper chip to chip, chip to wafer and wafer to wafer interconnects in through-silicon vias (TSV)

Abstract

A process of electrodepositing high purity copper in a via in a silicon substrate to form a through-silicon-via (TSV), including immersing the silicon substrate into an electrolytic bath in an electrolytic copper plating system in which the electrolytic bath includes an acid, a source of copper ions, a source of ferrous and/or ferric ions, and at least one additive for controlling physical-mechanical properties of deposited copper; and applying an electrical voltage for a time sufficient to electrodeposit high purity copper to form a TSV, in which a Fe⁺²/Fe⁺³ redox system is established in the bath to provide additional copper ions to be electrodeposited by dissolving copper ions from a source of copper metal.

Description

BACKGROUND[0001]1. Field of the Invention[0002]The invention relates to a process of electrolytically forming conductor structures from highly pure copper, more specifically to electrolytically forming conductor structures from highly pure copper in through-silicon vias (TSVs) when producing devices such as MEMS or semiconductor devices. Such TSVs are useful, e.g., in integrated circuits, in a stacked or 3D arrangement, in which the TSV provide electrical connection between the respective layers of the device, where the TSV have relatively large diameter, relatively great depth and a high aspect ratio.[0003]2. Description of Related Art[0004]The demands of fabricating cheaper, smaller and lighter electronic products offering better performance and increased functionality are continuously growing. The number of electronic device on a single chip is still rapidly increasing, and the ability of 2D layouts to accommodate these demands is being exceeded. According to industry roadmaps, i...

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Benefits of technology

[0007]In various of its embodiments, the present invention avoids the disadvantages of known processes and, more particularly, maximizes the electrodeposited filling of the TSVs with

Problems solved by technology

TSVs have been used for forming electrical connections between respective layers in a stacked or 3D arrangement in devices such as MEMS and semiconductor devices, but have suffered from various defects arising, at least partially, from difficulty in electroplating highly pure copper into the very large, high aspect ratio vias in the TSVs.

Attempts to electrodeposit high purity copper into such high aspect ratio TSVs have been partially successful, but have been plagued with problems arising from (a) internal stresses in the copper deposit which can result in wafer bending or deformation upon subsequent heating, (b) non-uniform deposits (i.e., grain boundaries, crystal structure defects, etc.), (c) inclu

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