Process for electrodeposition of copper chip to chip, chip to wafer and wafer to wafer interconnects in through-silicon vias (TSV)

Abstract

A process of electrodepositing high purity copper in a via in a silicon substrate to form a through-silicon-via (TSV), including immersing the silicon substrate into an electrolytic bath in an electrolytic copper plating system in which the electrolytic bath includes an acid, a source of copper ions, a source of ferrous and / or ferric ions, and at least one additive for controlling physical-mechanical properties of deposited copper; and applying an electrical voltage for a time sufficient to electrodeposit high purity copper to form a TSV, in which a Fe+2 / Fe+3 redox system is established in the bath to provide additional copper ions to be electrodeposited by dissolving copper ions from a source of copper metal.

Description

technical field [0001] The present invention relates to a process for electrolytically forming a conductor structure from high-purity copper, in particular to electrolytically forming conductors in through-silicon vias (TSV) from high-purity copper when manufacturing devices such as MEMS or semiconductor devices structure. Such TSVs are useful, for example, in integrated circuits in stacked or 3D arrangements, where the TSVs provide electrical connections between layers of the device, where the TSVs have relatively large diameters, relatively large depths, and high aspect ratio. Background technique [0002] There is a continuing need to manufacture cheaper, smaller and lighter electronic products that offer better performance and improved functionality. The number of electronic devices on a single chip is still growing rapidly, and the ability of 2D layouts to accommodate these demands is being exceeded. According to the industrial roadmap, in 2010 the integrated circuit...

AI Technical Summary

Problems solved by technology

Attempts to electrodeposit high-purity copper into such high-aspect-ratio TSVs have been partially successful, but have been plagued by problems caused by (a) internal stresses in the copper deposition that can cause wafer bowing or deformation, (b) non-uniform deposition (i.e., grain boundaries, crystal structure defects, etc.), (c) gas (porosity) in the body of electrodeposited copper and / or dopant of the plating bath liquid, and (d) Additional metal deposition at the entrance and exit of TSV perforations

[0004] Of these issues, the internal stress issue (a) may be the most problematic as it causes bowing and deformation throughout the silicon substrate where the TSVs are formed, and it can cause failure of the entire 3D arrangement

This failure may not occur until after the entire device has been fabricated, resulting in the loss not only of the failed silicon substrate, but of the entire device that had been incorporated into the silicon substrate at the time of failure

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