Multi-wafer 3D cam cell

Abstract

A multi-wafer CAM cell in which the negative effects of increased travel distance have been substantially reduced is provided. The multi-wafer CAM cell is achieved in the present invention by utilizing three-dimensional integration in which multiple active circuit layers are vertically stack and vertically aligned interconnects are employed to connect a device from one of the stacked layers to another device in another stack layer. By vertically stacking multiple active circuit layers with vertically aligned interconnects, each compare port of the inventive CAM cell can be implemented on a separate layer above or below the primary data storage cell. This allows the multi-wafer CAM structure to be implemented within the same area footprint as a standard Random Access Memory (RAM) cell, minimizing data access and match compare delays.

Description

FIELD OF THE INVENTION

[0001] The present invention relates to a semiconductor structure and a method of fabricating the same. More particularly, the present invention relates to a Content Addressable Memory (CAM) cell in which a compare port of the CAM cell is located in a separate wafer vertically abutting another wafer including the CAM cell's core latch, e.g., storage element. The present invention also provides a method of forming such a CAM cell in which three-dimensional (3D) integration is employed in forming the same.BACKGROUND OF THE INVENTION

[0002] Nearly every modern microprocessor employs a cache whereby some instructions and / or data are kept in storage that is physically closer and more quickly accessible than from the main memory. This type of storage is commonly known as a cache. When the cache is tightly integrated into the processors execution pipeline it's called an L1 (e.g., Level 1) cache.

[0003] FIG. 1 shows a system-level representation of a prior art microprocesso...

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