Method to fabricate high performance carbon nanotube transistor integrated circuits by three-dimensional integration technology

Abstract

Techniques for fabricating carbon nanotube-based devices are provided. In one aspect, a method for fabricating a carbon nanotube-based integrated circuit is provided. The method comprises the following steps. A first wafer comprising carbon nanotubes is provided. A second wafer comprising one or more device elements is provided. One or more of the carbon nanotubes are connected with one or more of the device elements by bonding the first wafer and the second wafer together. A carbon nanotube-based integrated circuit is also provided.

Description

FIELD OF THE INVENTION[0001]The present invention relates to carbon nanotube technology and more particularly, to techniques for fabricating carbon nanotube-based devices.BACKGROUND OF THE INVENTION[0002]Carbon nanotubes possess extraordinary electronic properties that are attractive for high-speed and high-performance circuits. One of the major challenges in utilizing devices and complex circuits involving carbon nanotubes lies in the incompatibility of the carbon nanotube growth conditions and the process limitation of current complementary metal-oxide-semiconductor (CMOS) technology. For example, chemical vapor deposition (CVD) grown carbon nanotubes require a growth condition of at least 600° C. for producing high quality nanotubes, which exceeds the temperature capacity of about 350° C. to about 400° C. for CMOS processes.[0003]One possible solution to work around this temperature limitation is to deposit preformed carbon nanotubes on the substrate from a solution. However, dur...

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Benefits of technology

[0006]The present invention provides techniques for fabricating carbon nanotube-based devices. In one aspect of the invention, a method for fabricating a carbon nanotube-based integrated circuit is provided. The method comprises the following steps. A first wafer comprising carbon nanotubes is provided. A second wafer comprising one or more device elements is provided. One or more of the carbon nanotubes are connected with one or more of the device elements by bonding the first wafer and the second wafer together.

Problems solved by technology

One of the major challenges in utilizing devices and complex circuits involving carbon nanotubes lies in the incompatibility of the carbon nanotube growth conditions and the process limitation of current complementary metal-oxide-semiconductor (CMOS) technology.

However, during the subsequent processing, the deposited carbon nanotubes may be destroyed via oxidation and the properties of the carbon nanotubes may also be altered due to surface treatments.

Another practical challenge of realizing integrated circuits based on carbon nanotubes is the alignment of carbon nanotubes with the rest of the circuit components.

While there has been much progress in controlling the growth orientation and / or the deposition location of nanotubes, their alignment with the rest of the circuits has not been addressed.

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