85results about How to "Reduce proximity effect" patented technology

A transparent touch panel according to this aspect of the present invention comprises a transparent substrate, a capacitive touch device positioned on the transparent substrate, an interfacial structure positioned on the capacitive touch device, and a display device positioned on the interfacial structure. The capacitive touch device includes a plurality of first sensing blocks positioned on the transparent substrate, a dielectric layer covering the first sensing blocks, a plurality of second sensing blocks positioned on the dielectric layer, a plurality of first wires positioned on the transparent substrate, and a plurality of second wires positioned on the dielectric layer. Preferably, the first sensing blocks and the second sensing blocks are interlaced, each first wire connects the first sensing blocks on the same column, and each second wire connects the second sensing blocks on the same row.

The present invention addresses many of the current limitations in sub-100 nm lithographic techniques by providing novel resists that achieve high sensitivity, high contrast, high resolution, and high dry-etch resistance for pattern transfer to a substrate. In one embodiment, the present invention provides a polymeric resist comprising an adamantyl component and a photoacid generating component.

A microphone enhancing device combines an automatic gain control, a band-limited compressor, and a gate in one very compact package that is small enough and efficient enough to plug into or be wired into the base of almost any microphone. A connector is provided on the device for removably connecting an infrared sensor directed parallel to the microphone. For gooseneck microphones the infrared sensor is also on a gooseneck. Low frequency tones are attenuated irrespective of attenuation of higher tones when a present audio level indicates that a speaker is too close to the microphone; this reduces proximity effect produced by microphones.

A method for formulating an exposure dose for an electron beam on a resist film for a pattern of geometric shapes which compensates for electron scattering effects utilizing hierarchial design data which is preserved to as great as an extent as possible in the computation of the exposure dose. The exposure dose is corrected for both the forward scatter and backscatter effects of the electron beam in which the design data is modified for interactions of shapes which are affected only over the forward scatter range. In another version of the method, a multiple Gaussian approximation is used where the short term Gaussian terms are treated as the forward scatter terms and the long term Gaussian terms are treated as the back scatter terms.

The present invention discloses a mask for reducing the proximity effect. The mask comprises a plurality of line-shaped features, a plurality of first assist features positioned between the line-shaped features and a plurality of second assist features positioned between the line-shaped feature and the first assist feature. The line-shaped feature corresponds to isolation trenches to be formed on a silicon wafer. The first assist feature is rectangular in shape and has a larger width at the direction perpendicular to the line-shaped features. The width of the second assist feature is smaller than two-fifths of the wavelength but larger than one-fourth of the wavelength of an exposure source. The size of the first assist feature and the second assist feature is so designed to be non-resolvable, while the line-shaped feature is resolvable and transferred to the silicon wafer.

A dummy via design for a dual damascene structure has a dielectric layer on a substrate, a dual damascene structure filled with a conductive material and inlaid in the dielectric layer, and a dummy via structure filled with a non-conductive material and inlaid in the dielectric layer. The dummy via structure has at least two dummy vias filled with the non-conductive material and located adjacent to two sides of the dual damascene structure respectively.

A rod antenna and antenna circuit are described which make use of negative feedback to reduce the Q of the antenna, but which also makes use of a different coil tapping arrangement to significantly reduce electric field susceptibility on the detected signal from the main coil as well as different biasing arrangements to reduce noise. More particularly, in some embodiments of the invention the main detector coil of the antenna has a centre tap that is AC grounded with signal taps then being taken from the opposite ends of the main coil, and being respectively fed to the inputs of a differential amplifier. The output of the differential amplifier is then fed to the magnetic circuit of the rod antenna via a second inductor winding that is magnetically coupled to the resonance circuit of the main antenna coil.

A photolithography and etch process sequence includes a photomask having a pattern with compensation features that alleviate patterning variations due to the proximity effect and depth of focus concerns during photolithography. The compensation features may be disposed near isolated or outermost lines of a device pattern. A photoresist pattern is formed to include the compensation features and the pattern etched to form a corresponding etched pattern including the compensation features. After etching, a protection material is formed over the layer and a trim mask is used to form a further photoresist pattern over the protection material. A subsequent etching pattern etches the protection material and removes the compensation features and results in the device lines being formed unaffected by proximity effects. Flare dummies may additionally be added to the mask pattern to increase pattern density and assist in endpoint detection. Flare dummies, like the compensation features, are subsequently removed by a photolithography and etching process sequence.

In order to prevent, among other things, fatigue failures in squirrel-cage rotors of electrical machines, the invention provides that the squirrel-cage winding is comprised of flexible conductors.

The grating polarization mask plate belongs to a farther optimization design of mask plate structure in projection optical photoetching system. It is characterized by that according to the characteristic line width of characteristic pattern on the mask plate, on the mask characteristic pattern etching a grating polarization structure with a certain width and depth, making grating structure for producing polarization light and traditional mask plate be combined into one body, and making the mask plate self-body have the function of outputting polarization light, and utilizing grating polarization mask to control the vector direction of electric field vector so as to control space coherent of electric field to attain the goal of raising resolution. Said invention also provides the application range of said projection photoetching equipment.

A method for forming a patterned target layer from a blanket target layer while employing a blanket photoresist layer in conjunction with an exposure method which is susceptible to a proximity effect employs when exposing the blanket photoresist layer to form an exposed blanket photoresist layer a main latent pattern and a second latent pattern adjacent the main latent pattern. Each patterned photoresist layer formed upon developing the main latent pattern is formed of a first linewidth such that not all of a first portion of the blanket target layer formed therebeneath is etched within an isotropic etchant which is employed for etching the blanket target layer to form the patterned target layer. In contrast, each patterned photoresist layer formed upon developing the second latent pattern is formed of a second linewidth such that all of a second portion of the blanket target layer formed therebeneath is etched within the isotropic etchant which is employed for etching the blanket target layer to form the patterned target layer. The method is particularly useful for efficiently forming a photomask while attenuating a proximity effect.

The invention relates to the technical field of planar transformers, in particular to a planar transformer, electronic equipment and a production method of the planar transformer. The planar transformer comprises a first magnetic core, at least one PCB (printed circuit board) winding, at least one pancake coil and a second magnetic core. The first magnetic core, all the PCB windings, all the pancake coils and the second magnetic cores are coaxially assembled into the planar transformer. On the one hand, a primary/secondary coil formed by the PCB windings and the pancake coils has higher overcurrent capability compared with the traditional winding coil; on the other hand, when the primary/secondary coil with more turns is required to be designed, the number of the turns of the pancake coilscan be increased/decreased transversely, the assembling of multiple layers of the primary/secondary coils can be relatively avoided; a proximity effect and stray capacitance are further reduced; thepower density is increased; and a temperature rise is reduced.

An integrated circuit and method of fabricating the same utilizing embedded silicon-germanium (SiGe) source/drain regions, and in which the proximity effect of nearby shallow trench isolation structures is reduced. Embedded SiGe source/drain structures are formed by selective epitaxy into recesses etched into the semiconductor surface, on either side of each gate electrode. The SiGe structures overfill the recesses by at least about 30% of the depth of the recesses, as measured from the interface between the channel region and the overlying gate dielectric at the edge of the gate electrode. This overfill has been observed to reduce proximity effects of nearby shallow trench isolation structures on nearby transistors. Additional reduction in the proximity effect can be obtained by ensuring sufficient spacing between the edge of the gate electrode and a parallel edge of the nearest shallow trench isolation structure.

A bus system for use in electrical distribution equipment includes a generally U-shaped arrangement of conductor conductors for supplying very high amperage (e.g., above 2000 amps) alternating current to the electrical distribution system. Compared to prior-art conductor arrangements, using the present arrangement, the conductor conductors of a phase can be fabricated from less copper, which is an expensive metal. They also achieve better thermal dissipation and current distribution and mitigate skin effects. As a result, resistive losses, which increase with increased temperature, are reduced.

One embodiment of the invention provides a system that uses pupil filtering to mitigate optical proximity effects that arise during an optical lithography process for manufacturing an integrated circuit. During operation, the system applies a photoresist layer to a wafer and then exposes the photoresist layer through a mask. During this exposure process, the system performs pupil filtering, wherein the pupil filtering corrects for optical proximity effects caused by an optical system used to expose the photoresist layer.

Disclosed is a method, system, and computer program product for performing edge optimization on an electronic design. According to some approaches, the number of edges and/or the length of edges within an IC design are configured for optimized manufacturability and yield of an integrated circuit. The edge optimization may occur in real-time during layout, placement, and/or routing, or occur in a post-optimization step.

A method of forming photo masks having rectangular patterns and a method for forming a semiconductor structure using the photo masks is provided. The method for forming the photo masks includes determining a minimum spacing and identifying vertical conductive feature patterns having a spacing less than the minimum spacing value. The method further includes determining a first direction to expand and a second direction to shrink, and checking against design rules to see if the design rules are violated for each of the vertical conductive feature patterns identified. If designed rules are not violated, the identified vertical conductive feature pattern is replaced with a revised vertical conductive feature pattern having a rectangular shape. The photo masks are then formed. The semiconductor structure can be formed using the photo masks.

Disclosed is an improved method, system, and computer program product for performing layout, placement, and routing for electronic designs. According to some approaches, multiple objects are considered as a collective object or shape, based upon the proximity of one or more of the objects to one or more other objects. The type and/or configuration of the collective object is based, for example, upon the type of rule that is being considered for the layout, placement, or routing operation.

An optical proximity correction mask used for fabricating a color filter includes a substrate, a mask pattern and a mending pattern. Wherein, the mask pattern is disposed on the substrate. The mask pattern and the transferred pattern, being transferred to the color filter, are not matched and cause occurrence of a light leaking region in the color filter. The mending pattern is disposed over the substrate around the periphery of the mask pattern and corresponds to the light leaking region.

The invention discloses a single-event-proximity-effect-resistant static storage unit of a physical space interleaving type. The static storage unit comprises a transistor of a storage unit A and a transistor of a storage unit B, wherein the transistor of storage unit A is composed of a first access transistor AMG1 of the storage unit A, a second access transistor AMG2 of the storage unit A, a first pull-up transistor AMP1 of the storage unit A, a second pull-up transistor AMP2 of the storage unit A, a first pull-down transistor AMN1 of the storage unit A and a second pull-down transistor AMN2 of the storage unit A, which are arranged on a silicon substrate; and the transistor of the storage unit B is composed of a first access transistor BMG1 of the unit B, a second access transistor BMG2 of the unit B, a first pull-up transistor BMP1 of the unit B, a second pull-up transistor BMP2 of the unit B, a first pull-down transistor BMN1 of the unit B and a second pull-down transistor BMN2 of the unit B, which are arranged on the silicon substrate. Proximity effect can be effectively reduced by adopting the invention, and therefore, the critical charges of SEU (Single Event Upset) of the storage units are enlarged to enhance the single event resistance.