A gate wire including a gate line, a gate
electrode, a gate pad and a gate line connector and a common
signal wire are formed on a substrate, and a gate insulating layer is formed over the gate wire and the common
signal wire. A
semiconductor layer and an
ohmic contact layer are sequentially formed on the gate insulating layer, a data wire including a source and a drain
electrode, a data line, a data pad and a data line connector and a pixel
electrode are formed thereon. The thickness of the data wire and the pixel electrode is equal to or less than 500 Å. A
passivation layer is formed on the data wire and the pixel electrode, a redundant data wire is formed thereon, and a redundant gate pad and a redundant gate line connector are formed. The redundant data wire is electrically connected to the data wire through the contact holes in the
passivation layer, and the redundant gate pad and the redundant gate line connector are electrically connected to the gate pad and the gate line connector respectively through the contact holes in the
passivation layer and the gate insulating layer. The redundant gate line connector and the redundant data line connector are connected to each other to short the gate and the data wires. After an alignment layer is formed and rubbed, the edge of the panel is
cut away to remove the gate line connector and the data line connector.