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41 results about "Cad tools" patented technology

4. nanoCAD. nanoCAD is a free, industry-standard CAD tool that has a variety of APIs and a powerful table editor. It contains many tools for both 2D and 3D modeling, with multiple methods of creating geometric shapes available.

Methods and systems for viewing geometry of an object model generated by a CAD tool

A system for remotely viewing geometry of an object model generated by a CAD tool hosted on a server computer on a network. The system has an image viewer accessible via a client computer on the network and an image server operatively connected between the image viewer and the CAD tool. The system receives an object model selection, provides the CAD tool with an ICAD application associated with the selection, commands the CAD tool to generate an object model having one or more elements using the ICAD application, displays on the client computer a structure identifying the one or more elements, receives a request to view a selected element, commands the CAD tool to generate an image file describing geometry of the selected element in response to the request, and displays the geometry of the selected element on the client computer in accordance with the image file.
Owner:THE BOEING CO

Method and apparatus for adding advanced instructions in an extensible processor architecture

A system for adding advanced instructions to a microprocessor includes a language for formally capturing the new instructions and a method for generating hardware implementations and software tools for the extended processors. The extension language provides for additions of VLIW instructions, complex load / store instructions, more powerful description styles using functions, more powerful register operands, and a new set of built-in modules. The method is capable of generating fully-pipelined micro-architectural implementations for the new instructions in the form of synthesizable HDL descriptions which can be processed by standard CAD tools. The method is also capable of generating software components for extending software development tools for the microprocessor with new instructions.
Owner:TENSILICA

System for real time, non-invasive metrology of microfluidic chips

A system integration of multicomponent technologies includes an automated microfluidic probe station and the use of that station for the systematic study of nonideal, nonhomogeneous biological fluids such as blood in microfluidic chips. The probe station provides for real-time, non-invasive metrology of microfluidic chips employing optical coherence tomography and optical Doppler tomography to allow for collection of flow data at any location or depth within a microfluidics chip. Also included is a programmable fluidic loader and actuator platform as part of the probe station, and a semi-automated rapid prototyping tool used to fabricate the microfluidic chips measured on the probe station. The resulting data library produced by measurements on the probe station contains all the necessary information needed to develop mature, accurate microfluidic modeling and simulation CAD tools.
Owner:RGT UNIV OF CALIFORNIA

Scripted, hierarchical template-based IC physical layout system

InactiveUS7178114B2Quickly and easily to commandQuickly and easily generateComputer programmed simultaneously with data introductionCAD circuit designComputer Aided DesignTemplate based
A computer-aided design tool for automatically generating a layout for an electronic device to be formed by a set of objects implemented within an integrated circuit, receives input from a user defining a device template specifying shapes, dimensions and relative positions within the layout of the objects forming the device. Some of the object dimensions and / or relative positions are specified as functions of values of input parameters to be supplied by the user. When the user supplies the input parameters, the CAD tool evaluates the functions to determine the object dimensions and / or positions that are functions of the input parameters and then generates a layout for the electronic device wherein object shapes, dimensions and relative positions are as specified in the device template and consistent with the function evaluations. The device template may also include instructions for modifying the layout, for example, indicating that copies of an object are to form an array in the layout, that copies of one object are to fill another object, that an object is to be added to the layout having a shape that is a Boolean function of other objects, and that objects are to be added to or removed from the layout.
Owner:SYNOPSYS INC

Method for Replicating and Synchronizing a Plurality of Physical Instances with a Logical Master

Design Data Management uses one copy of common data sets along with a plurality of instances, while continuing to utilize the existing design databases and existing CAD tools. Allowing a minimum amount of user intervention to create and maintain the common data set, Design Data Management employs replicating common data sets into one or more clone data sets. The method preferred provides for replicating and synchronizing one or more data sets with a master data set, comprises providing data design management of a master data set and at least one clone data set, and copying a master physical design data set into one or more physical instances to enable customization of said one or more physical instances. The master data set describes at least one of: a design component, a circuit macro, and a circuit entity, and comprises logical data sets, and it comprise physical design data sets. This permits all existing verification processes that are normally executed against the common data set to also be equally applied to the clones of said data set by way of automatic synchronization between of the common dataset and the clones.
Owner:IBM CORP

Method and apparatus for adding advanced instructions in an extensible processor architecture

ActiveUS7346881B2Improves both the configurable and extensible aspectsImprove performanceInstruction analysisNext instruction address formationExtension languageProcessor register
A system for adding advanced instructions to a microprocessor includes a language for formally capturing the new instructions and a method for generating hardware implementations and software tools for the extended processors. The extension language provides for additions of VLIW instructions, complex load / store instructions, more powerful description styles using functions, more powerful register operands, and a new set of built-in modules. The method is capable of generating fully-pipelined micro-architectural implementations for the new instructions in the form of synthesizable HDL descriptions which can be processed by standard CAD tools. The method is also capable of generating software components for extending software development tools for the microprocessor with new instructions.
Owner:TENSILICA

Method for processing biomedical images

The present invention relates to a method for highlight and to diagnose regions of interest in biomedical radiographic images, useful in the context of a CAD tool processing operating as second reader during the normal clinical and screening routine, so reducing the costs of management of the “double reading” procedure.
Owner:MEDICAD

Method for generating optimized, constant curvature 2D or 3D roller profile curves and corresponding device

The invention relates to a method for generating an optimized 2D or 3D roller profile curve (5), having a prescribed desired 2D or 3D roller profile curve (5) of a roller profile (5) that changes along a rolled material feed direction (X) and actuating a flexible roller profile device, in which profiling rollers (11) can be adjusted in a computer-controlled manner during a roller profiling process. The method for generating the optimized 2D or 3D roller profile curve comprises the following: a) entering the desired 2D or 3D roller profile curve (5) by means of CAD tools; b) calculating the optimized 2D or 3D roller profile curve (5) from the input and desired 2D or 3D roller profile curve (5) using rounding algorithms, wherein the rounding algorithms round off the 2D or 3D profile curves (5) at a substantially constant curvature, so that the optimized 2D or 3D roller profile curve (5) is generated accordingly, substantially avoiding an uneven curvature; c) confirming or modifying a region of the optimized 2D or 3D roller profile curve (5); and d) saving the optimized 2D or 3D roller profile curve (5).
Owner:DATA M SHEET METAL SOLUTIONS

Method for replicating and synchronizing a plurality of physical instances with a logical master

Design Data Management uses one copy of common data sets along with a plurality of instances, while continuing to utilize the existing design databases and existing CAD tools. Allowing a minimum amount of user intervention to create and maintain the common data set, Design Data Management employs replicating common data sets into one or more clone data sets. The method preferred provides for replicating and synchronizing one or more data sets with a master data set, comprises providing data design management of a master data set and at least one clone data set, and copying a master physical design data set into one or more physical instances to enable customization of said one or more physical instances. The master data set describes at least one of: a design component, a circuit macro, and a circuit entity, and comprises logical data sets, and it comprise physical design data sets. This permits all existing verification processes that are normally executed against the common data set to also be equally applied to the clones of said data set by way of automatic synchronization between of the common dataset and the clones.
Owner:IBM CORP

Methods and apparatus for embedding an error correction code in memory cells

ActiveCN106021636AError detection/correctionError correction/detection using block codesError checkingComputer Aided Design
A computer-aided design (CAD) tool may identify don't care bits in configuration data. The don't care bits in the configuration data may change polarity without affecting the functionality of the circuit design. The CAD tool may compute an error check code (e.g., parity bits for a two-dimensional parity check) and insert the error check code into the configuration data. As an example, the CAD tool may replace don't care bits in the configuration data with the error code. The configuration data may be stored in configuration memory cells on a programmable integrated circuit, thereby implementing the circuit design with the error code on the programmable integrated circuit. During execution, the programmable integrated circuit may execute error checking and detect and correct errors in the configuration data based on the embedded error code.
Owner:ALTERA CORP

Engineering validation and audit tool independent of design and product management platforms

ActiveUS20160283871A1Cryptography processingResourcesProduct stewardshipQuality rating
A quality validation tool in a form of a computer program, installable on a specific hardware and or workstations which supports industrial CAD tools and PLM tools, the quality validation tool is executable independent of CAD platforms, Non-CAD platforms and or PLM platforms, wherein an engineering information resides in a geometry extractor while a plurality of engineering rules reside in a check validator. The engineering information is encrypted and decrypted. The tool has capability to perform quality audit, while keeping CAD form and detailing unknown to auditor. Validation report with quality rating is generated.
Owner:TATA TECH PTE

System and method analyzing design elements in computer aided design tools

System and method for analyzing design elements in a CAD tool design. A configuration element generator encodes information in a configuration command to generate a configuration element associated with at least one of the design elements. A sequencer, coupled to the configuration element generator, tags the configuration element with a sequence number. A computer memory, coupled to the sequencer, stores the configuration element. A processor, coupled to the computer memory, applies, to the design element that is of interest, each stored said configuration element associated with the design element of interest, in an order indicated by the sequence number. A configuration element is an encoding of data comprising formatted information associated with a design.
Owner:HEWLETT PACKARD DEV CO LP

Density checking method in territory verification

The invention relates to a quick density checking method in territory verification, belonging to the field of territory verification in IC CAD tools. Density checking is a figure operation in a design rule checking (DRC) in the IC CAD tool territory verification, and the primary meaning of density checking is to check area percent of a certain layer of figure in the whole zone area; some density checking asks for that area computation is available when a computing layer figure is located in another corresponding figure layer. The description method is as follows: density is available when a computing figure layer is inside of a corresponding figure layer, but in the condition, density is difficult to calculate. The invention provides a density checking and realizing method aiming to the above conditions, so that computational efficiency of density checking with computation layers can be greatly improved.
Owner:北京华大九天科技股份有限公司

Method for computer aided design of semiconductor integrated circuits

In transistor layout design, a plurality of distances Lfig1, Lfig2, Lfig3 from a gate electrode of a transistor to the edge of a diffusion layer are displayed by multiple lines according to a variation amount of a transistor characteristic with the use of a CAD tool. A layer for defining an isolation region between adjacent transistors is extended automatically by the CAD tool. Accordingly, even in the case where the transistor characteristic varies depending on the distance from the gate electrode of the transistor to the edge of the diffusion layer, the isolation region between the adjacent transistors can be layouted and designed optimally with no measurement of the distance by designer's visual observation necessitated.
Owner:SOCIONEXT INC

Composite grinding machining feature automatic identification method based on part engineering image

ActiveCN110942107AHigh pixel-level precisionLightweight development and applicationImage enhancementImage analysisEngineeringTrack algorithm
The invention discloses a composite grinding machining feature automatic identification method based on a part engineering image. The method comprises two main body steps of geometric contour extraction and process feature matching. The external features and the internal features are respectively represented by a solid line frame and a dotted line frame, and the geometric contour extraction is divided into two stages, so that the problem of automatic identification of intersection features generally existing in an automatic feature identification technology is solved. The feature geometric contour extraction is based on a boundary tracking algorithm, an effective contour of each feature represented by four angular point pixels is obtained, a CNN classifier is utilized to classify whether internal features exist in a part or not, and finally effective automatic recognition of multiple manufacturing features is sequentially carried out according to geometric information. The method doesnot depend on any CAD tool or data exchange standard, various typical composite grinding machining features can be automatically extracted, high pixel-level precision is guaranteed, and development and application based on the method are lighter and convenient to transplant.
Owner:SHANGHAI UNIV

Detection and removal of hazards during optimization of logic circuits

A method of generating a hazard-free representation of a logic circuit that can leverage the powerful and mature synchronous-circuit CAD synthesis tools. In a representative embodiment of the method, an initial representation of a specified asynchronous logic circuit is synthesized using one of such CAD tools. The initial representation is then analyzed to identify hazardous transitions and modified, e.g., by iteratively inserting additional logic aimed at preventing the identified hazardous transitions from producing glitches, until a hazard-free representation of the specified asynchronous logic circuit is produced.
Owner:SKYWORKS SOLUTIONS INC

CAD method for arranging via-holes, a CAD tool, photomasks produced by the CAD method, a semiconductor integrated circuit manufactured with photomasks and a computer program product for executing the CAD method

A design method encompasses: determining a direction of a subject wiring level in a multi-level interconnection of semiconductor integrated circuit as a subject-level priority direction; designing a layout of the subject wiring level, by placing a subject-level strip extending along the subject-level priority; generating a subject-level extension extending in a different direction of the subject-level priority direction, from a termination of the subject-level strip; allocating via-holes in the subject-level extension; and designing a layout of a neighboring wiring level of the subject wiring level, by placing a neighboring-level strip extending along the same direction as the subject-level extension extends, so that a termination of the neighboring-level strip can include the via-holes.
Owner:KK TOSHIBA

Cycle cutting with timing path analysis

The timing cycles in a circuit design are identified and cut such that timing constraint paths in the circuit design are preserved. Timing cycles in the circuit design may be identified by traversing an adjacency list data structure, in which elements of the circuit design are represented as vertices interconnected by edges. Timing constraint paths may be distinguished from false timing paths using timing analysis, such as a greatest common path heuristic. Timing constraint paths may be marked as “constrained” to prevent these paths from being cut. With the cycles and timing constraint paths identified, cuts may be selected that cut the identified timing cycles while preserving the timing constraint paths. The cycle cuts allow the circuit design to be correctly processed within a conventional CAD tool design flow.
Owner:UNIV OF UTAH RES FOUND

Method and apparatus for performing hardware assisted placement

A method for designing a system on a target device is disclosed. A first plurality of components in the system are assigned to be placed by an computer aided design (CAD) tool based on a criterion. A second plurality of components in the system are assigned to be placed by a hardware placement unit based on the criterion. Placement results from the CAD tool and the hardware placement unit are used to generate a placement solution for the system on the target device. Other embodiments are described and claimed.
Owner:ALTERA CORP

Method for quickly compiling aircraft assembly process file

The invention belongs to the technical field of aircraft assembly process file compilation. The invention discloses a method for quickly compiling an aircraft assembly process file. The method includes the steps: integrating CAD software provided with a customized CAD tool with a CAPP system, using a customized CAD tool to extract three-dimensional model information of a product, enabling the three-dimensional model information to form an XML process text according to a standard process parameter format, then importing the XML process text into a CAPP system, and achieving transmission and interaction of the process information. According to the method, manual extraction of the three-dimensional model information of the product from CAD software can be omitted, and automatic import of theextracted three-dimensional model information of the product can be realized, so that the compiling efficiency and quality of the assembly file are effectively improved.
Owner:CHENGDU AIRCRAFT INDUSTRY GROUP

Method of enforcing a contract for a CAD tool

A method for enforcing a contract for a computer-aided-design (CAD) tool is provided. In this method, a first payment for the CAD tool is made in accordance with the contract. The first payment is associated with user access to the CAD tool. At this point, the CAD tool can be used, wherein the computer system running the CAD tool includes criteria for requesting at least one additional payment for the CAD tool. Each additional payment is associated with generating an output. The computer system is responsive to one or more trigger conditions corresponding to the criteria. A payment request is received when an output generated by the CAD tool satisfies a trigger condition. For example, one trigger condition adds a watermark to the output for identifying the output as having been produced by the CAD tool.
Owner:SYNOPSYS INC

Method and apparatus for reusing subparts of one mechanical design for another mechanical design

InactiveUS7010473B1Computation using non-denominational number representationComputer aided designEngineeringMechanical design
A mechanical design reuse method includes having a CAD tool replicates a subset of a first modeling representation of a first mechanical design, in response to having received instructions that identify a subpart of the first mechanical design. The reuse method further includes having the CAD tool merges the replicated subset into a second modeling representation of a second mechanical design to effectuate the reuse of the identified subpart of the first mechanical design in the second mechanical design. In one embodiment, the modeling representations are dependent graphs, and the subsets being replicated and merged are sub-graphs of the dependent graphs. The dependent graphs and sub-graphs include nodes directly associated with the subparts of the designs, nodes on which the directly associated nodes are dependent, and arcs linking the nodes together in accordance with their dependency on each other. In one embodiment, the replicate and merging process also provides for a designer the option to transform certain design variables having constant values assigned to become design variables eligible to have their values variably assigned, and vice versa.
Owner:AUTODESK INC

Development general data conversion middleware adaptable to various CAD tools and conversion method

The invention relates to development general data conversion middleware capable of adapting to various CAD tools, and belongs to the technical field of computer aided design (CAD). According to the invention, the middleware adopts a modular design concept, through an API (Application Program Interface) provided by the CAD tool and a universal interface developed in the middleware, rapid integration of the new CAD tool and the PLM system is supported, and the integration efficiency is obviously improved compared with that of a traditional scheme. The middleware comprises a data analysis layer, a general data model layer, a data mapping layer and an output adaptation layer. According to the method, repeated development of integrated software for different CAD tools or different PLM systems is not needed, the efficiency and compatibility of tool integration and system integration are improved, and the development cost and the maintenance cost are reduced.
Owner:NANJING GLAWAY SOFTWARE CO LTD

Method of orthopedic treatment

A method of orthopedic treatment includes steps of: by using a computer aided design (CAD) tool based on profile data that is related to a to-be-treated part of a bone of a patient, obtaining a model of a preliminary instrument that substantially fits the to-be-treated part; by using the CAD tool, obtaining a model of a patient specific instrument (PSI) based on the model of the preliminary instrument; producing the PSI based on the model of the PSI, the PSI being adjustable; performing medical operation on the to-be-treated part, and then attaching the PSI to the to-be-treated part; after attaching the PSI to the to-be-treated part, adjusting the PSI such that the PSI is adapted to real conditions of the to-be-treated part.
Owner:CHANG GUNG MEMORIAL HOSPITAL +1

An Approximate Calculation Circuit Reliability Evaluation Method Based on Signal Probability

The invention discloses an approximate calculation circuit reliability evaluation method based on signal probability, comprising: inputting a circuit netlist file, analyzing the circuit netlist file, extracting circuit connection structure information according to the content of the netlist file; A CAD tool that obtains the signal probabilities of all input terminals in the circuit and the probability of different input combinations of each gate; initializes the probability and reliability of the original input signal of the circuit; calculates each gate based on the probability of the original input signal The reliability of the original output terminal; calculating the corresponding circuit reliability of each input combination and adding the circuit reliability obtained by each input combination to obtain the average value to obtain the reliability of the entire circuit. The method of the invention has the advantages of short time consumption, wide application range and high evaluation result accuracy when evaluating the reliability of the approximate circuit.
Owner:SHANGHAI UNIVERSITY OF ELECTRIC POWER

Design automation methods for 3D integrated circuits and devices

Methods of designing a 3D Integrated Circuit including: partitioning at least one design into at least two levels, a first level and a second level, where the first level includes first transistors, where the second level includes second transistors is on top of the first level; providing placement data of the second level; performing a placement of the first level using a placer program executed by a computer, where the placement of the first level is based on the placement data, where the placer is part of a Computer Aided Design (CAD) tool, and where the first level includes first routing layers; performing a routing of the first level using a router {part of the CAD tool or another CAD tool) executed by a computer, where at least one metal routing layer is disposed in-between the first transistors and the second transistors, and the second level includes repeating structures.
Owner:MONOLITHIC 3D INC

3D printing resin for manufacturing low-loss antenna and application of 3D printing resin

The invention discloses 3D printing resin for manufacturing a low-loss antenna and application of the 3D printing resin. The 3D printing material comprises a light-cured resin prepolymer, a photoinitiator, a reactive diluent, a dispersing agent, a laser-activatable metal compound and low-loss polymer powder. The preparation method of the material comprises the following steps: preparing the light-cured resin base material; doping a low dielectric loss material; doping a catalyst capable of being activated by laser; and performing defoaming treatment. The processing method of the low-loss antenna comprises the following steps: 1, constructing an antenna model by using a CAD tool; 2, carrying out antenna matrix 3D printing by using the prepared light-cured resin material; 3, conducting laser activation; and 5, metalizing the conductive circuit of the antenna. According to the functional 3D printing material for manufacturing the low-loss antenna, the capability of manufacturing electronic circuit products through 3D printing is greatly improved, and the functional 3D printing material can be applied to the fields of aerospace, 5G communication, intelligent automobiles and the like.
Owner:SOUTHEAST UNIV

CAD cutter path offset method based on arc transition and self-intersection processing

The invention discloses a CAD cutter path offset method based on arc transition and self-intersection processing. The method comprises the following steps: firstly, obtaining and disassembling an original polyseme primitive into ordered sub-primitives; then normal offset is carried out, and when adjacent offset sub-primitives are processed, transition arcs are trimmed or inserted according to whether the adjacent offset sub-primitives intersect or not, so that continuous smooth transition of G1 is realized; aiming at a negative radius arc generated by the ultra-large offset, performing conversion by adopting a mechanism of taking an absolute value, reversing a direction and compensating an angle; discretizing all the primitives and binding original primitive identification information for discrete line segments; then Boolean operation is carried out to remove a self-intersection path; and finally, according to the identification information, clustering and restoring the discrete line segments into continuous straight lines or arc entities. According to the method, the problems of unsmooth path transition, ultra-large offset path breakage and Boolean operation precision loss are effectively solved, and the cutter path which is high in quality, free of self-intersection and capable of keeping the original precision is generated.
Owner:TIANDI CHANGZHOU AUTOMATION +1