Integrated circuit floorplanning method based on best fit heuristic sequence and multi-objective organizational evolution

An integrated circuit and heuristic technology, applied in the fields of electrical digital data processing, special data processing applications, instruments, etc., can solve problems such as large amount of calculation and what weight to assign

Active Publication Date: 2014-04-09
XIDIAN UNIV
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Problems solved by technology

When solving a new problem, it is impossible to know what weights should be assigned to it to obtain the optimal result. In addition, the single-objective method can only solve

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  • Integrated circuit floorplanning method based on best fit heuristic sequence and multi-objective organizational evolution
  • Integrated circuit floorplanning method based on best fit heuristic sequence and multi-objective organizational evolution
  • Integrated circuit floorplanning method based on best fit heuristic sequence and multi-objective organizational evolution

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Embodiment Construction

[0053] The VLSI layout planning problem studied by the present invention refers to placing all modules in the first quadrant when the optimal adaptation heuristic sequence requires all modules to be in the most suitable position, and requires them to There will be no overlap between them, so that the area of ​​the envelope surrounding all modules is minimized and the line length is minimized. VLSI layout problems are divided into many types. The multi-objective, soft rectangular module VLSI layout planning problem solved by the present invention aims to make the area utilization ratio of the chip optimal and the line length the shortest, and to standard The five soft rectangle module problem sets in the problem bank MCNC are tested.

[0054] Such as figure 1 as shown,

[0055] The main flowchart step features are:

[0056] Step 101: start the integrated circuit layout method based on optimal adaptation heuristic sequence and multi-objective tissue evolution;

[0057] Step...

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Abstract

The invention discloses an integrated circuit floorplanning method based on a best fit heuristic sequence and multi-objective organizational evolution, and belongs to the technical field of physical design floorplanning. The method uses the best fit heuristic sequence for encoding and decoding, is combined with a multi-objective organizational evolutionary algorithm, and is used for solving the very large scale integration floorplanning problem. The method is characterized in that firstly each individual is initialized, then each individual is coded and decoded through the best fit heuristic sequence, and finally, a designed split operator, a designed annexation operator and a designed training operator are used for optimizing the multi-objective organization. Verification results show that the integrated circuit floorplanning method has advantages on two important aspects of methods and effectiveness for evaluating and solving the very large scale integration floorplanning problem, namely, the area utilization ratio and optimal line length of an optimal chip, and the method effectively solves the very large scale integration floorplanning problem and can be expanded to solve other multi-objective organizational optimization problems.

Description

technical field [0001] The present invention relates to a method of layout planning for physical design, in particular to an integrated circuit layout based on Best Fit Heuristic Sequence (BFHS) and Multi-objective Organizational Evolutionary Algorithms (MOEA). graph method. Background technique [0002] Floorplanning is a key link in the physical design of very large scale integration (VLSI), and its results have an important impact on the final chip size and global interconnection structure. With the rapid development of technology, the complexity of chip design is increasing rapidly, and the requirements for chip size and internal interconnection performance are also getting higher and higher, which makes the role of layout planning particularly important. For the floorplanning problem, many scholars have proposed a variety of algorithms using different mathematical tools, including the minimum partition algorithm, hierarchical design method, analytical algorithm and sto...

Claims

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Application Information

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IPC IPC(8): G06F17/50
Inventor 刘静焦李成朱园王景润马文萍马晶晶
Owner XIDIAN UNIV
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