Integrated Circuit Layout Method Based on Optimal Fit Heuristic Sequence and Tissue Evolution

An integrated circuit and heuristic technology, applied in the direction of electrical digital data processing, special data processing applications, instruments, etc., can solve the problems of destroying the arbitrariness and continuity of the shape change of the soft rectangular module, the increase of calculation time, and the low layout efficiency.

Active Publication Date: 2017-01-25
XIDIAN UNIV
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Problems solved by technology

[0004] All of these methods are one-way layout methods. In the layout process, the layout is only faced to the module sequence, and the feedback information of the already placed modules is rarely used to provide effective heuristic guidance for the modules to be placed. This makes the layout The graph efficiency is not high, and the calculation time increases exponentially with the layout scale
Their treatment of soft rectangular modules is also very rough. They just randomly select several candidate modules to replace soft rectangular modules, and then make layout according to the layout method of hard modules. Discrete points, which destroy the arbitrariness and continuity of the shape change of the soft rectangular module, do not match the actual situation

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  • Integrated Circuit Layout Method Based on Optimal Fit Heuristic Sequence and Tissue Evolution
  • Integrated Circuit Layout Method Based on Optimal Fit Heuristic Sequence and Tissue Evolution
  • Integrated Circuit Layout Method Based on Optimal Fit Heuristic Sequence and Tissue Evolution

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Embodiment Construction

[0068] The VLSI layout problem studied by the present invention refers to placing all modules in the first quadrant when the optimal adaptation heuristic sequence requires all modules to be in the most suitable position, and requires them to There will be no overlap between them, so that the area of ​​the envelope surrounding all modules is minimized. The VLSI layout problem is divided into many kinds. The VLSI layout problem of single object, soft rectangular module and soft rectangular module and hard straight line boundary module that the present invention solves is mixed, and the goal is to make the area utilization rate of the chip Optimal, and tested on the datasets of two standard question banks MCNC and GSRC.

[0069] The present invention initializes each individual according to the characteristics of the representation module, and each individual contains three elements: BFHS, COST, Treated (record whether the individual has been trained). Search whether each indivi...

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Abstract

The invention discloses an integrated circuit layout method based on a best fit heuristic sequence and organizational evolutionary algorithms, and belongs to the technical field of physical design layout planning. The best fit heuristic sequence is utilized for carrying out encoding and decoding, is combined with the organizational evolutionary algorithms and is used for solving the super-large-scale integrated circuit layout. The integrated circuit layout method is characterized in that firstly, units are initialized, secondly, the best fit heuristic sequence is utilized for carrying out encoding and decoding on the units, and lastly, the organization is optimized through the designed split operator, the designed annexation operator and the designed training operator. The verification result shows that one important aspect of evaluating the effectiveness of solving the super-large-scale integrated circuit layout of the method is the optimal chip area utilization rate solving, and the integrated circuit layout method has the advantages that the integrated circuit layout method is an effective method for solving the super-large-scale integrated circuit layout problem and can be expanded to solve the multi-goal super-large-scale integrated circuit layout problem.

Description

technical field [0001] The present invention relates to a method of physical design layout planning, in particular to an integrated circuit layout method based on Best Fit Heuristic Sequence (BFHS) and Organizational Evolutionary Algorithms (OEA). Background technique [0002] Floorplanning is a key link in the physical design of very large scale integration (VLSI), and its results have an important impact on the final chip size and global interconnection structure. With the rapid development of technology, the complexity of chip design is increasing rapidly, and the requirements for chip size and internal interconnection performance are also getting higher and higher, which makes the role of layout planning particularly important. For the floorplanning problem, many scholars have proposed a variety of algorithms using different mathematical tools, including the minimum partition algorithm, hierarchical design method, analytical algorithm and stochastic optimization algorith...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50
Inventor 刘静焦李成朱园王景润马文萍马晶晶
Owner XIDIAN UNIV
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