Time sequence optimization method based on dummy

An optimization method and timing technology, applied in special data processing applications, instruments, electrical digital data processing, etc., can solve the problems of complex implementation, inability to guarantee consistency and observability, accuracy and low repair efficiency, and achieve the cost of implementation Low cost, reduced design complexity, and a wide range of configurations

Active Publication Date: 2021-07-27
PHYTIUM TECH CO LTD
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Problems solved by technology

[0006] However, the traditional technical solutions, including the above solutions, are very complicated to implement. Either the original hardware topology needs to be changed, or the accuracy and repair efficiency are low, and the consistency and considerable repair before and after repair cannot be guaranteed. sex

Method used

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  • Time sequence optimization method based on dummy
  • Time sequence optimization method based on dummy
  • Time sequence optimization method based on dummy

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Embodiment Construction

[0038] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0039] Such as figure 1 Shown, a kind of timing optimization method based on dummy of the present invention, its step comprises:

[0040] Step S1: Build the dummy library;

[0041] Step S2: Analyze the physical design sequence and prepare data for formulating a suitable repair strategy;

[0042] Step S3: process the data in step S2, classify timing violations, and divide them into data path (data path) and clock path (clock path) according to different repair paths; wherein, the data path data path can be used to repair hold time (hold ) violations, the clock path clock path can be used to fix setup and hold violations.

[0043] Step S4: Repair the data path (data path), that is, insert the dummy in parallel, and realize the repair of the illegal path through the dummy with an equivalent Delay;

[0044] Step S5: Repair the clock p...

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Abstract

The invention discloses a time sequence optimization method based on dummy. The time sequence optimization method comprises the following steps: S1, constructing a dummy library; S2, analyzing a physical design time sequence, and preparing data for formulating a proper repair strategy; S3, processing the data in the step S2, classifying time sequence violations, and dividing the time sequence violations into data paths and clock paths according to different repair paths; wherein the data path can be used for repairing hold time violation, and the clock path can be used for repairing setup time and hold time violation; S4, repairing the data path by inserting the dummy; S5, repairing the clock path by inserting the dummy; and S6, performing static time sequence STA analysis again, and completing time sequence violation repairing. The method has the advantages of being simple in principle, low in implementation cost, capable of rapidly and accurately repairing time sequence violation and the like.

Description

technical field [0001] The invention mainly relates to the technical field of high-performance chip design, in particular to a dummy-based timing optimization method. Background technique [0002] For high-performance chip design, in order to improve performance, it is often accompanied by high frequency, which means higher requirements for timing. However, due to the increase in frequency, it will become more and more difficult to converge the timing, and the repair of timing violations will also become more and more difficult, especially the critical path will become very "sensitive". Seemingly a small change may affect the critical path. It is a major change, which virtually increases the difficulty of physical design and increases the design iteration cycle. [0003] For example, Chinese patent application CN202010791428.8 discloses a timing repair method for chip circuits. The timing repair method includes: determining the virtual area corresponding to the drive unit i...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/3312G06F30/398
CPCG06F30/3312G06F30/398Y02T10/40
Inventor 蒋剑锋栾晓琨王翠娜孙永丰邓宇边少鲜
Owner PHYTIUM TECH CO LTD
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