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Automatic physical unit insertion method based on original layout planning

A physical unit and layout planning technology, applied in the direction of electrical digital data processing, special data processing applications, instruments, etc., can solve the problem of consuming design and wiring resources

Active Publication Date: 2020-06-09
NAT UNIV OF DEFENSE TECH
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Therefore, only pin cells will consume design routing resources

Method used

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  • Automatic physical unit insertion method based on original layout planning
  • Automatic physical unit insertion method based on original layout planning
  • Automatic physical unit insertion method based on original layout planning

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Embodiment Construction

[0050] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0051] Such as figure 1 As shown, the automatic physical unit insertion method based on the original layout planning of the present invention includes:

[0052] Step S1: After designing the layout, expand all sub-modules at the top level, and record each sub-module and the instantiation name of the hard macro module that needs to be fixed at the top level to Document 1;

[0053] Step S2: Read the document 1 to obtain the information on the layout barrier layer of each hard macromodule;

[0054] Step S3: Report the full-chip congestion situation, record the coordinates and Box parameters of all hotspots, generate a wiring blocking rectangular Box of equal size, and name it according to certain rules;

[0055] Step S4: generate document 2 by recording the instantiation names, position coordinates and Box parameters of all the above Bo...

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Abstract

The invention discloses an automatic physical unit insertion method based on original layout planning. The method comprises the steps: S1, expanding the top layer of a chip, and recording the name ofa macro module in a document 1; s2, reading the document 1, and obtaining information of a hard macro unit Box; s3, reporting chip congestion information, and establishing a blocking rectangle Box ata hot spot; s4, recording all Box names and parameters into a document 2; s5, establishing a Box0 array with the distance range from the physical unit to the boundary of the chip; s6, Box1 of the unitspacing range is established at the same position of each Box0; s7, selecting Box4 capable of laying units from each Box1, and finding Box5 with the maximum area from the Box4; s8, calculating a central coordinate of each unit in each Box 5; s9, determining a central coordinate of the blank Box 9 calculation unit in the blank Box 9 calculation unit; s10, deleting the Block and inserting the Blockinto the physical unit; s11, ending is carried out. The method has the advantages of being simple in principle, easy to operate, capable of improving overall physical design efficiency and the like.

Description

technical field [0001] The invention mainly relates to the technical field of integrated circuit design, in particular to an automatic physical unit insertion method based on the original layout planning. Background technique [0002] In the physical design of integrated circuits, the physical unit is different from the functional unit. It will not change the function of the design, but it plays an important role in ensuring the manufacturability, yield and reliability of the chip. It plays an important role in the electrostatic protection ability. Inserting a certain number of physical units according to a certain spacing requirement in the physical design stage is the key to its function. According to the standard cell library provided by the process manufacturer and the specific requirements of the design, usually the number of physical cells inserted in the full chip is small and the distance between adjacent cells is a range value. Moreover, compared with general hard...

Claims

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Application Information

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IPC IPC(8): G06F30/392
Inventor 刘必慰杨隆俊宋睿强胡春媚吴振宇郭阳
Owner NAT UNIV OF DEFENSE TECH
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