129results about How to "Capacitance" patented technology

By decreasing the threshold voltage shift due to the potential change of the cells adjacent in a word line direction, the reliability of a flash memory can be enhanced. Memory cells of a flash memory are formed in p-type wells of a semiconductor substrate and include gate insulator films, floating gates, high-K insulator films, and control gates (word lines). The floating gates and control gates (word lines) are isolated by high-K insulator films. The plurality of memory cells arrayed in row a direction are isolated by isolation trenches extending in a column direction. In the isolation trenches, a silicon oxide film is embedded. In the silicon oxide film, an air gap is provided. A lower end of the air gap extends near to the bottom of the isolation trench, and its upper end extends further above the upper surface of the high-K insulator film covering the floating gate.

The invention provides a manganese dioxide / carbon nanocomposite and a preparation method and application thereof. The preparation method comprises the following concrete steps: mixing an aqueous solution of permanganate, a carbon carrier and an aqueous solution of a divalent manganese salt; carrying out a reaction to produce a precipitate; and carrying out washing and drying so as to obtain the manganese dioxide / carbon nanocomposite. The preparation method has the advantages of easiness, rapidness, environment friendliness and easy realization of scale-up synthesis. The prepared manganese dioxide / carbon nanocomposite is applicable to a super-capacitor, a metal-air battery and a fuel battery.

Method for sputtering from a dielectric target (9) in a vacuum chamber (2) with a high frequency gas discharge, the target (9) being mounted on a cooled metallic back plate (10) and this back plate forming an electrode (10) supplied with high frequency, includes a target thickness (Td) profiled (15) differently over the surface such that in the regions of a desired decrease of the sputtering rate the target thickness (Td) is selected to be greater than in the remaining regions.

In a semiconductor device, capacitance between copper interconnections is decreased and the insulation breakdown is improved simultaneously, and a countermeasure is taken for misalignment via by a manufacturing method including the steps of forming an interconnection containing copper as a main ingredient in an insulative film above a substrate, forming insulative films and a barrier insulative film for a reservoir pattern, forming an insulative film capable of suppressing or preventing copper from diffusing on the upper surface and on the lateral surface of the interconnection and above the insulative film and the insulative film, forming insulative films of low dielectric constant, in which the insulative film is formed such that the deposition rate above the opposing lateral surfaces of the interconnections is larger than the deposition rate therebelow to form an air gap between the adjacent interconnections and, finally, planarizing the insulative film by interlayer CMP.

A metal contactless smart card includes a first metal layer having a first slit, a second layer, a radio-frequency integrated circuit chip module, and an inlay having an antenna. A nonconductive insert may be fitted in the slit. The first metal layer may include an inlay recess where the inlay may be received and a through-hole where the chip may be inserted. The second layer of the smart card may be made of metal and may also include a slit.

Exemplary embodiments of the invention provide a micromechanical electrostatic resonator which designs high frequency, increases a ratio of output voltage to input voltage, and designs low drive voltage or reduced power consumption. A micromechanical electrostatic resonator of exemplary embodiments includes a plate-shaped vibration body, a pair of electrodes arranged oppositely to each other at both sides of the vibration body with a gap from an outer circumferential portion of the vibration body, a feeding device to apply in-phase alternating-current power to the pair of electrodes, and a detecting device to obtain an output corresponding to a change in capacitance between the vibration body and the electrodes. The planar shape of the vibration body takes a shape having a curved outline which comprises a neck portion.

A semiconductor device includes: an inductor (1) provided with a conductor interconnection formed spirally on a semiconductor substrate (10); and a shield (6a) that is provided with a continuous conductor interconnection provided along the outer periphery of the spiral pattern of the inductor (1) while opening a portion of the conductor interconnection, and that is electrically connected to ground potential.

The semiconductor device comprises: a semiconductor substrate (N+ substrate 110) containing a first conductivity type impurity implanted therein; a second conductivity type impurity-implanted layer (P+ implanted layer 114) at relatively high concentration, formed on the semiconductor substrate (N+ substrate 110); a second conductivity type impurity epitaxial layer (P− epitaxial layer 111) at relatively low concentration, formed on the second conductivity type impurity-implanted layer (P+ implanted layer 114); and a field effect transistor 100 (N-channel type lateral MOSFET 100)composed of a pair of impurity diffusion regions (N+ source diffusion layer 115 and N− drain layer 116) provided in the second conductivity type impurity epitaxial layer (P− epitaxial layer 111) and a gate electrode 117 provided over a region sandwiched with the pair of impurity diffusion regions (N+ source diffusion layer 115 and N− drain layer 116).

Provided are a conductive film and a touch panel in which an extraction electrode that is formed in a visible region is inconspicuous to improve visibility, the initial capacitance between electrodes is increased to improve the accuracy of detection, and the electrodes are formed on only one main surface of a base to reduce costs. The conductive film includes a transparent base, first and second electrodes 32A and 32B that are formed on a main surface of the transparent base so as to face each other, and an extraction electrode 34 that is formed on the main surface of the transparent base and extends from the second electrode 32B. The first electrode 32A has a shape which surrounds a portion of the second electrode 32B. At least the extraction electrode 34 is formed in a mesh pattern 38 including a plurality of grids 36 which are formed by thin metal wires.

The invention is directed to improve characteristics of an HBT (Hetero-junction Bipolar Transistor). An HBT has a collector layer, a base layer, and an emitter layer formed in order on a main surface of a substrate made of a compound semiconductor and a collector electrode, a base electrode, and an emitter electrode electrically connected to the collector layer, the base layer, and the emitter layer, respectively, and further has an emitter contact layer formed between the emitter electrode and the emitter layer. The plane shape of the emitter contact layer and the emitter electrode is an almost annular shape surrounding the base electrode in a plane parallel with the main surface of the substrate, and the lower limit of the emitter contact layer is 1.2 μm or larger.

A magnetoinductive flowmeter for measuring the flow rate of a flowing, conductive medium with a capacitive measuring apparatus for detecting empty pipes is provided. In order to improve the detection of empty pipes and, in particular, the capacitive coupling to the medium, the invention provides for the measuring apparatus for detecting empty pipes to comprise a sheet-like electrode in each case and a counterelectrode which form a measurement capacitance CMess which is dependent on the medium and on the degree of filling of the measuring tube; for the measuring tube to have a wall thickness which is reduced in order to maximize the measurement capacitance CMess at least in the region of the electrode and the counterelectrode; and for the measuring tube to be surrounded by a metal supporting housing, wherein, in order to maintain the pressure resistance of the measuring tube, a hollow-walled supporting body for minimizing the influence of parasitic capacitances on the measurement capacitance CMess is arranged in each case in the region of the reduced wall thickness between the electrode and the inner wall of the supporting housing and between the counterelectrode and the inner wall of the supporting housing and supports the measuring tube against the supporting housing in each case.

In a high frequency LDMOS transistor, a gate structure is formed on a substrate. A drain, doped with first type impurities at a first concentration, is formed on the substrate spaced apart from the gate structure. A buffer well, doped with the first type impurities at a second concentration lower than the first concentration, surrounds side and lower portions of the drain. A lightly doped drain, doped with the first type impurities at a third concentration lower than the second concentration, is formed between the buffer well and the gate structure. A source, doped with the first type impurities at the first concentration, is formed on the substrate adjacent to the gate structure and opposite to the drain with respect to the gate structure. Accordingly, an on-resistance decreases while a breakdown voltage increases in the LDMOS transistor without increasing a capacitance between the gate structure and the drain.

The semiconductor device includes multilayer wirings of a dual damascene structure. The multilayer wirings include a first wiring layer formed on a semiconductor substrate and a second wiring layer formed on the first wiring layer. The first wiring layer includes a first insulation film, plural first vias provided in the first insulation film, a second insulation film provided on the first insulation film, and a first wiring provided on the first vias and connected to those first vias in the second insulation film. The second wiring layer includes a third insulation film, plural second vias provided in the third insulation film, an adhesive layer provided on the third insulation film, a fourth insulation film provided on the adhesive layer, and a second wiring provided on the second vias and connected to those second vias in the fourth insulation film. In the first wiring layer, the aspect ratio L of a wiring having the minimum wiring width and the via aspect ratio V are in a relationship of L≧V and in the second wiring layer, the aspect ratio L of a wiring having the minimum wiring width and the via aspect ratio V is in a relationship of L<V.

A buffer cell and an inverter cell are embedded in advance in an internal open space of each of mega-cells and IO cells composing a semiconductor integrated circuit. Thereafter, in cases where it is expected that a cross-talk noise is generated in a signal transmitting through a particular wire of the semiconductor integrated circuit, one mega-cell or one IO cell, which is placed in a position nearest to a generation position of the cross-talk noise, is selected from the mega-cells and the IO cells, and the buffer cell or the inverter cell embedded in the selected mega-cell or the selected IO cell is inserted into the particular wire. Therefore, because the capacitance between the particular wire and each wire adjacent to the particular wire is reduced, the cross-talk noise can be reduced.

A charge trapping layer in an element isolation region and that in an isolation region between a memory transistor and a selection transistor are removed so that the charges are not injected or trapped in the regions. Also, in an element isolation region, gate electrodes of each memory transistor are united at a position higher than a gate electrode of the selection transistor from a surface of a silicon substrate in an element isolation region, thereby reducing the capacitance between the memory transistor and the selection transistor.

A cold cathode field emission device having an electron emission layer (14), an insulating layer and a gate electrode (12) which are laminated one on another with the insulating layer positioned between the gate electrode, and the electron emission layer (14), and further having an opening portion which penetrates through at least the insulating layer and the electron emission layer, the electron emission layer having an edge portion for emitting electrons, the edge portion being projected on a wall surface of the opening portion, and the electron emission layer being connected to a power source through a resistance layer (23).

The present invention provides a touch substrate and a touch screen. The touch substrate comprises first electrodes and electrodes which intersect with each other, each first electrode includes a plurality of first metal meshes, adjacent first metal meshes are connected through a connection portion, each second electrode includes a plurality of second metal meshes, adjacent second metal meshes are connected through a connection bridge, the first metal meshes, the second metal meshes and the connection portion are in the same layer, and an insulation layer is provided between the layer in which the connection portion is located and the layer in which the connection bridge is located, at least a part of edges of the first metal mesh is provided with a first side strip thereat, the first side strip is adjacent to a corresponding second metal mesh and is connected to the first metal mesh.

The semiconductor device comprises a silicon substrate 14 having a step formed in the surface which makes the surface in a flash memory cell region 10 lower than the surface in a peripheral circuit region 12; a device isolation region 20a formed in a trench 18 in the flash memory cell region 10; a device isolation region 20c formed in a trench 24 deeper than the trench 18 in the peripheral circuit region 12; a flash memory cell 46 including a floating gate 32 and a control gate 40 formed on the device region defined by the device isolation region 20a; and transistors 62, 66 formed on the device regions defined by the device isolation region 20c.

An object of the present invention is to suppress deterioration of display quality due to difference in wiring resistance and capacitance between the layers in a display device having a layered wiring structure. In a display device having a layered wiring structure of P layers, and employing a Q-column reversal driving method in which a polarity of a video signal is reversed every Q source bus lines (SL), the plurality of source bus lines SL are wired to the plurality of layers such that taking source bus lines (SL) of a number equal to a double of a least common multiple of P and Q as one group, the number of source bus lines (SL) to which positive video signals are applied matches the number of source bus lines (SL) to which negative video signals are applied in each of the layers in each of horizontal scanning periods.

An MR effect element that can obtain the sufficient back flux-guide effect under the condition of reducing the capacitance between the upper and lower electrode layers is provided. The element comprises: an MR effect multilayer provided on the lower electrode layer; an insulating layer surrounding a rear side surface and side surfaces opposed to each other in track width direction of the MR effect multilayer; and an upper electrode layer provided on the MR effect multilayer and the insulating layer, the insulating layer having a concave portion filled with a portion of the upper electrode layer, the concave portion positioned near the rear side surface of the MR effect multilayer, and a bottom point of a concave of the concave portion positioned at the same level or a lower level in stacking direction compared to an upper surface of the free layer.

A semiconductor device includes trenches defined in a substrate, buried bit lines partially filling the trenches, a first source / drain layer filling remaining portions of the trenches on the buried bit lines, stack patterns having a channel layer and a second source / drain layer stacked therein and bonded to the first source / drain layer, wherein the channel layer contacts with the first source / drain layer, and word lines crossing with the buried bit lines and disposed adjacent to sidewalls of the channel layer.

The present disclosure discloses an array substrate, touch display panel and touch display device. The array substrate comprises a substrate, a display region and a non-display region surrounding the display region. A driver chip is provided in the non-display region. The display region comprises a plurality of data lines. Each of the plurality of data lines is electrically connected to the driver chip via a respective one of a plurality of first connection lines; and a plurality of touch electrode blocks. The plurality of touch electrode blocks are electrically connected to the driver chip via a plurality of touch signal lines. In the non-display region, the plurality of touch signal lines are not overlapped with the plurality of first connection lines in a direction perpendicular to the substrate.