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High frequency MOS transistor, method of forming the same, and method of manufacturing a semiconductor device including the same

a technology of high-frequency metal oxide semiconductors and transistors, which is applied in the direction of semiconductor devices, electrical equipment, basic electric elements, etc., can solve the problems of affecting the performance of ldmos transistors, fatal signal loss through a channel in real transistors, and breakdown voltages that are generally incompatible with transistor on-resistance, so as to improve transistor electrical characteristics, reduce transistor on-resistance, and reduce the effect of transistor capacitance between the gate structure and drain

Inactive Publication Date: 2006-01-19
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The present invention provides a high frequency transistor that can operate at a high breakdown voltage and has a low on-resistance. The transistor has a unique structure that includes a gate structure, a drain, a buffer well, a lightly doped drain, a source, and a contact region. The transistor can be manufactured using a specific method that allows for the formation of the unique structure. The invention also provides a semiconductor device that includes the high frequency transistor. The technical effects of the invention include improved performance and reliability of high frequency transistors and semiconductor devices.

Problems solved by technology

In particular, the breakdown voltage and the on-resistance greatly affect the performance of the LDMOS transistor when the LDMOS transistor is operated at a high frequency.
As a result, an excessively low off-resistance causes a leakage current, and an excessively high on-resistance leads to a fatal signal loss through a channel in real transistors.
However, the breakdown voltage is generally incompatible with the on-resistance of a transistor.
A high breakdown voltage necessarily causes a high on-resistance of a transistor, and a low on-resistance of a transistor necessarily requires a low breakdown voltage.
When the breakdown voltage is low, a capacitance between a gate and a drain of a transistor is increased, so that an operation failure frequently occurs in a high frequency transistor.

Method used

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  • High frequency MOS transistor, method of forming the same, and method of manufacturing a semiconductor device including the same
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  • High frequency MOS transistor, method of forming the same, and method of manufacturing a semiconductor device including the same

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embodiment 1

[0043]FIG. 1 is a cross sectional view illustrating a high frequency LDMOS transistor in accordance with a first exemplary embodiment of the present invention.

[0044] Referring to FIG. 1, a semiconductor layer 12 is formed through an epitaxial process on a semiconductor substrate 10 heavily doped with P-type impurities. In the present embodiment, the semiconductor layer 12 on the semiconductor substrate 10 is formed to a thickness in a range from about 1 μm to about 10 μm, and is doped with P-type impurities at a relatively lower concentration than the semiconductor substrate 10.

[0045] A gate structure 30 is formed on the semiconductor layer 12. The gate structure 30 includes a gate insulation pattern 24 having a uniform thickness, a gate electrode pattern 26 and a hard mask pattern 28 that are sequentially stacked on the semiconductor layer 12 in the order named above. A spacer 50 is formed on a side surface of the gate structure 30.

[0046] N-type impurities are implanted at a sur...

embodiment 2

[0067] FIGS. 7 to 11 are cross sectional views illustrating processing steps for a method of manufacturing a semiconductor device having both a high frequency LDMOS transistor and a CMOS transistor according to a second exemplary embodiment of the present invention.

[0068] Referring to FIG. 7, a semiconductor layer 102 is formed to a thickness of about 1 μm to about 10 μm on a semiconductor substrate 100 heavily doped with P-type impurities through an epitaxial process, and the P-type impurities are implanted through a surface of the semiconductor layer 102 more lightly than the substrate 100 in-situ with the above epitaxial process or in an additional process different from the epitaxial process. In the present embodiment, the semiconductor layer 102 is divided into three distinct regions: an LDMOS region in which the high frequency LDMOS transistor is to be formed, an NMOS region in which an NMOS transistor of a CMOS transistor is formed and a PMOS region in which a PMOS transisto...

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Abstract

In a high frequency LDMOS transistor, a gate structure is formed on a substrate. A drain, doped with first type impurities at a first concentration, is formed on the substrate spaced apart from the gate structure. A buffer well, doped with the first type impurities at a second concentration lower than the first concentration, surrounds side and lower portions of the drain. A lightly doped drain, doped with the first type impurities at a third concentration lower than the second concentration, is formed between the buffer well and the gate structure. A source, doped with the first type impurities at the first concentration, is formed on the substrate adjacent to the gate structure and opposite to the drain with respect to the gate structure. Accordingly, an on-resistance decreases while a breakdown voltage increases in the LDMOS transistor without increasing a capacitance between the gate structure and the drain.

Description

CROSS REFERENCE TO RELATED APPLICATION [0001] This application claims priority under 35 USC § 119 to Korean Patent Application No. 2004-55061, filed on Jul. 15, 2004, the contents of which are herein incorporated by reference in their entirety for all purposes. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to a high frequency metal oxide semiconductor (MOS) transistor, a method of forming the same and a method of manufacturing a semiconductor device including the same. More particularly, the present invention relates to a high frequency lateral double-diffused (LD) MOS transistor, a method of forming the same, and a method of manufacturing a semiconductor device having the LDMOS transistor. [0004] 2. Description of the Related Art [0005] Semiconductor transistors can generally be classified as a bipolar junction transistor (BJT) and a field effect transistor (FET) in accordance with the type of charge carrier thereof. [0006] While ...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L29/78H01L21/8238H01L21/336
CPCH01L21/823807H01L21/823814H01L29/7835H01L29/0847H01L29/66659H01L27/0922H01L21/2253H01L27/0928
Inventor LEE, SUN-HAK
Owner SAMSUNG ELECTRONICS CO LTD
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