High frequency MOS transistor, method of forming the same, and method of manufacturing a semiconductor device including the same

Abstract

In a high frequency LDMOS transistor, a gate structure is formed on a substrate. A drain, doped with first type impurities at a first concentration, is formed on the substrate spaced apart from the gate structure. A buffer well, doped with the first type impurities at a second concentration lower than the first concentration, surrounds side and lower portions of the drain. A lightly doped drain, doped with the first type impurities at a third concentration lower than the second concentration, is formed between the buffer well and the gate structure. A source, doped with the first type impurities at the first concentration, is formed on the substrate adjacent to the gate structure and opposite to the drain with respect to the gate structure. Accordingly, an on-resistance decreases while a breakdown voltage increases in the LDMOS transistor without increasing a capacitance between the gate structure and the drain.

Description

CROSS REFERENCE TO RELATED APPLICATION [0001] This application claims priority under 35 USC § 119 to Korean Patent Application No. 2004-55061, filed on Jul. 15, 2004, the contents of which are herein incorporated by reference in their entirety for all purposes. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to a high frequency metal oxide semiconductor (MOS) transistor, a method of forming the same and a method of manufacturing a semiconductor device including the same. More particularly, the present invention relates to a high frequency lateral double-diffused (LD) MOS transistor, a method of forming the same, and a method of manufacturing a semiconductor device having the LDMOS transistor. [0004] 2. Description of the Related Art [0005] Semiconductor transistors can generally be classified as a bipolar junction transistor (BJT) and a field effect transistor (FET) in accordance with the type of charge carrier thereof. [0006] While ...

AI Technical Summary

Benefits of technology

[0027] In another aspect, the present invention is directed to a method of manufacturing a semiconductor device. A semiconductor substrate on which a semiconductor layer is formed is provided, and a surface of the substrate is divided into a lateral double-diffused metal oxidation of silicon (LDMOS) region in which an LDMOS transistor is formed, a PMOS region in which a P-type transistor is formed and an NMOS region in which an N-type transistor is formed. N-type impurities are partially implanted into the LDMOS region and the PMOS region at a second concentration, so that a buffer N-well is formed on a first portion of the LDMOS region and the N-well of the P-type transistor is formed on the PMOS region. A P-well of the N-type transistor is formed on the NMOS region by partially implanting P-type impurities into the NMOS region. First, second and third gate structures are formed on the LDMOS region spaced apart from the buffer N-well, on the NMOS region and the PMOS region, respectively. A lightly doped drain (LDD) is formed on the LDMOS region by implanting N-type impurities into the LDMOS region between the first gate structure and the buffer N-well, and a lightly doped N-type area is formed on the NMOS region around the second gate structure by implanting the N-type impurities into the NMOS region at a third concentration lower than the second concentration. A source and a drain of the LDMOS transistor are formed at surface portions of the LDMOS region and source and drain regions of the N-type transistor are formed at surface portions of the NMOS region by partially implanting N-type impurities into the LDMOS and NMOS regions of the substrate at a first concentration higher than the second concentration. The source of the LDMOS transistor is formed adjacent to the first gate structure on a second portion of the LDMOS region, opposite to the first portion of the LDMOS region with respect to the first structure. The drain of the LDMOS transistor is formed on a substrate corresponding to the buffer N-well, and the source and drain of the NMOS transistor are formed adjacent to the second gate structure and opposite to each other with respect to the second gate structure. A source and a drain of the P-type transistor are formed at surface portions of the PMOS region by partially implanting P-type impurities into the PMOS region adjacent to the third gate structure and opposite to each other with respect to the third gate structure. According to the present invention, the buffer well surrounds the drain of the transistor, so that an on-resistance of the transistor is decreased and electrical characteristics of the transistor are improved. In addition, the buffer well is not overlapped with the gate structure of the transistor, so that a capacitance between the gate structure and the drain is not increased despite the buffer well. Therefore, frequency characteristics of the transistor are not deteriorated due to the buffer well.

Problems solved by technology

In particular, the breakdown voltage and the on-resistance greatly affect the performance of the LDMOS transistor when the LDMOS transistor is operated at a high frequency.

As a result, an excessively low off-resistance causes a leakage current, and an excessively high on-resistance leads to a fatal signal loss through a channel in real transistors.

However, the breakdown voltage is generally incompatible with the on-resistance of a transistor.

A high breakdown voltage necessarily causes a high on-resistance of a transistor, and a low on-resistance of a transistor necessarily requires a low breakdown voltage.

When the breakdown voltage is low, a capacitance between a gate and a drain of a transistor is increased, so that an operation failure frequently occurs in a high frequency transistor.

Images