125 results about "Signal propagation delay" patented technology

A method of routing a message from a source node to a destination node in an adhoc wireless network comprising a plurality of nodes, comprising the steps of; transmitting a first message from the source node to the destination node, receiving said first message at said destination node, transmitting a second message from said destination node in response to the first message and, wherein at least one of said first message and said second message is sent between the source and destination nodes via a plurality of paths comprising at least one intermediate node, selecting a path for communication between the source node and the destination node using an indication of the time taken for at least one of said second and first messages to propagate between each node on each path.

Methods and apparatus for compensating the effects of display signal propagation delay in a display panel are disclosed. The apparatus comprises circuitry in addition to conventional display driver circuitry for delaying display line timing signals by an amount approximating the delay found in corresponding display lines. By delaying display line timing signals, for example in a column driver, by an time approximately equal the delay experienced in a corresponding row enable signal line, capacitors associated with the display pixels charge more fully resulting in a more vivid display image. Methods for compensating the effects of display signal propagation delay involve generating a plurality of delayed display timing signals and activating display lines in response to those delayed timing signals.

A method and apparatus is disclosed for improving high frequency performance of an amplifier, such as for example, a current mirror. In one embodiment, a delay element is introduced in a current mirror signal path to account for signal propagation delay that may exist in one or more alternative signal paths. The delay element maintains desired phase alignment at a cascade node of the current mirror thereby establishing, in one embodiment, the cascode node (V_c) in an AC ground state. To extend current mirror high frequency capability an embodiment is disclosed having cross-coupled capacitors, active elements, or one or more other devices configured to provide positive feedback to one or more current mirror inputs. The positive feedback may be selectively configured to increase the operational bandwidth of the current mirror.

An integrated communication system includes a satellite portion and a terrestrial portion. A plurality of timeslots are allocated for transmission and reception of data by the various components of the satellite portion and terrestrial portion. The allocation of timeslots to the satellite portion and the terrestrial portion may be predetermined or dynamically allocated based on traffic loads, time of day, day of week, and the like. Communication may be accomplished on a single frequency with the appropriate allocation of timeslots. The system includes delay compensation to accommodate signal processing delays and signal propagation delays. For example, a satellite may be instructed to terminate transmission prior to the end of its allocated timeslot to permit the signal from the satellite to propagate to its intended destination within the allocated timeslot to thereby avoid spillover into the next timeslot. This avoids interference between various elements of the communication system.

In a circuit and method for correcting skew among a plurality of communication channels used in communicating with a memory circuit, and in a memory controller and memory controlling method, and in a memory system and method, the circuit for correcting skew includes a transmitting circuit for transmitting a reference signal to input ends of the plurality of channels and through the plurality of channels, and a plurality of receiving circuits for receiving at the input ends of the plurality of channels a respective plurality of reflected signals, the reflected signals being reflected from respective output ends of the plurality of channels. A detection circuit receives the reflected signals and detects relative signal propagation time differences between the plurality of channels. A delay circuit coupled to at least one of the channels sets a signal propagation delay in the at least one of the channels based on the detected relative signal propagation time differences.

Method and apparatus for finding an assignment of voltages to all power domains of an integrated circuit such that the power consumption of an integrated circuit design is minimized and timing requirements (signal propagation delay or slack) are met. This is done by modeling both internal and external signal paths in an integrated circuit which has a number of power domains. The relationship between slack and voltage for the external and internal signal propagation paths is modeled, typically as a linear approximation. The integrated circuit design is then abstracted to a simplified form in terms of power domain relations and a model is created and solved iteratively using, e.g., linear programming, of different voltage levels for each power domain and including the slack values and their relationship between the changes in voltage and slack, for both the internal and external paths.

Embodiments of the invention relate to an apparatus and a method for testing a plurality of devices under test. The apparatus for testing a plurality of devices under test comprises a common device output line and a driver unit configured to provide a stimulus to the DUTs. The driver unit is configured such that the stimulus reaches different DUTs at different times, thereby creating stimuli time shifts at the DUTs. The apparatus further comprises a receiver unit electrically coupled to the common device output line and a plurality of DUTs connections, electrically coupled to the common device output line, so that DUT terminals of the plurality of DUTs are electrically coupleable via the common device output line to the receiver unit. Output signal propagation delays for DUT output signals, propagating from the DUT connections to the receiver unit, are adapted to the stimuli time shift, such that a test of DUTs which have identical stimulus response delays, results in a temporally aligned superposition of the DUT output signals at the receiver unit.

An optical waveguide having a optical waveguide path capable of securing a high light propagation characteristic regardless of the type of a supporting base, provided with a multilayer circuit board, an optical waveguide path arranged on the multilayer circuit board, a light receiving element, IC chips, and a light emitting element, the optical waveguide path formed on a transparent substrate excellent in flatness and transferred to the multilayer circuit board. The light propagation loss becomes small, and a signal to be transmitted at a high speed being transmitted as a light signal and a signal which can be transmitted at a relatively low speed being transmitted as an electrical signal, whereby the signal propagation delay which becomes the problem when a signal is transmitted by only electrical wiring is overcome, and the influence of electromagnetic noise becomes small.

A system and a method are disclosed for performing a timing or signal propagation delay analysis on a circuit. The disclosure includes representing a drive logic stage as a representative linear circuit driven by a current source. The current source is represented as a function of a current at a constant value, a start time, a tail-start time, and a time constant of an equivalent capacitive circuit. Once the current source model is constructed, a logic stage can be analyzed for timing or signal propagation delay using conventional linear circuit analysis techniques. The disclosure also is applicable to resistance capacitance (“RC”) interconnect circuits using a current source model in which an RC load is represented as an effective capacitance and the current source for use in a linear analysis is constructed using an iterative approach.

Described are methods for accurately measuring the skew of clock distribution networks on programmable logic devices. Clock distribution networks are modeled using a sequence of oscillators formed on the device using configurable logic. Each oscillator includes a portion of the network, and consequently oscillates at a frequency that depends on the signal propagation delay associated with the included portion of the network. The various oscillator configurations are defined mathematically as the sum of a series of delays, with the period of each oscillator representing the sum. The respective equations of the oscillators are combined to solve for the delay contribution of the included portion of the clock network. The delay associated with the included portion of the clock network can be combined with similar measurements for other portions of the clock network to more completely describe the network.

Roughly described, signal propagation delay values are estimated for a plurality of interconnects in a circuit design. For each interconnect, the propagation delay value(s) are estimated in dependence upon a preliminary approximate determination of whether the signal propagation delay is dominated more by an interconnect capacitance term or by an interconnect capacitance and resistance product term. If it is dominated more by the interconnect capacitance term, then the parameter values used for a minimum propagation delay calculation are obtained assuming a smallest capacitance process variation case and the parameter values used for a maximum propagation delay calculation are obtained assuming a largest capacitance process variation case. If the signal propagation delay is dominated more by the interconnect capacitance and resistance product term, then the opposite assumptions are made. Preferably the approximate determination is made by comparing Rint to k*Rd.

The output of a pre-decoder 10A is provided, on one side, to a main decoder 22 with the input of negative logic and on the other side, to a main decoder 21 with the input of positive logic through an inverting circuit 40. The number of gate stages from the output of the pre-decoder 10A to the output of the main decoder 21 is three which is equal to the number of gate stages from the output of the pre-decoder 10A to the output of the main decoder 22.

After predicting a relationship between a design margin set against a fabrication variation in design of an LSI and a yield, a specific design margin for attaining a given yield is calculated based on the predicated relationship. The yield is a delay yield obtained by cumulating a signal propagation delay time thereby achieving a probability that a signal propagated through a logic circuit of the LSI is delayed by a given amount of time, and the design margin is a derating factor indicating a ratio between the signal propagation delay time and a standard value of the signal propagation delay time.

A test method and a measuring device for acoustic delay of a gas ultrasonic flowmeter relate to the technology for detecting ultrasonic wave propagation time of ultrasonic flowmeters, in particular to the technology for measuring time errors of electronic circuit signal propagation delay time, transducer signal delay time, signal sampling point delay time and signal cable delay time, and are suitable for sound velocity detection of various diameters of ultrasonic flowmeters. The test method for the acoustic delay is a measuring method for contrasting and proving acoustic delay data of a detected meter through a detected high-accuracy standard gas sound velocity measuring device, a computer and upper computer software according to standard sound velocity of a place where the detected gas ultrasonic flowmeter is located.

Techniques are disclosed for providing relatively short distances between multi-channel transmitter optical subassemblies (TOSAs) and associated transmit connecting circuit in order to reduce losses due to signal propagation delays, also sometimes referred to as signal flight time delays. In an embodiment, a TOSA includes a plurality of laser assemblies disposed along a same sidewall of the TOSA along a longitudinal axis. The TOSA may be disposed within an optical transceiver housing in a transverse orientation, whereby a longitudinal center line of the multi-channel TOSA is substantially perpendicular to the longitudinal axis of the optical transceiver housing. The TOSA may be positioned adjacent an end of the optical transceiver housing having a transmit connecting circuit. Thus each of the plurality of laser assemblies may be positioned at a relatively short distance, e.g., 120 microns or less, away from the transmit connecting circuit.

A system and method for determining a signal propagation delay between a transmitter and a receiver, and for adjusting a transmission time based on the propagation delay. A central station inserts a marker into a transmitted signal at a time corresponding to a received timing signal. The MCT receives the signal from the central station and determines a time difference between receipt of the marker and the detection of the time interval event. A transmission by the MCT is adjusted by an amount of time proportional to the time difference.

This invention discloses a composite distributed dielectric structure. It comprises one or more conductor layers, one or more dielectric layers distributed on the conductor layers, and one or more conductor traces distributed on the dielectric layers. One or more dielectric plates can be further around the conductor traces. The dielectric layers or plates may or may not have plural dielectric materials therein, respectively described in two embodiments. Each conductor trace lies on a dielectric material without crossing two different dielectric materials. Two or more dielectric layers may be stacked on the conductor layers The invention provides a low cost and practical dielectric structure for interconnect systems to reduce dielectric loss, cross talk, and signal propagation delay and to well control the impedance matching while maintaining proper heat dissipation and noise reduction at high frequency transmission.

This invention relates to a fast booking out of multiple access methods, including: central control node has been successful under the current access and the number of nodes installed idle channel resources of the competition slot number; center control nodes in the first or second Channel announced appointments, whit the mentioned competition slot; nodes go to compete booking in the first channel then shoe to, the second channel; Center control nodes receive the booked on the first signal channel, receive at the second channel at the same time access results and the success of nodes to access the distribution channel resources; each node in the distribution channel resources were Send business groups without conflict. This invention effectively eliminate the signal propagation delay channel throughput of the adverse effects and reduce the appointment of hidden terminal and exposed terminals, packet transmission in the business also eliminates collisions, particularly suitable for the transmission delay as a communication link on the use of Channel Access Multiple Access Method.

The invention discloses a scheduling system and a decision-making method for service deployment and migration in a mobile edge calculation environment. According to the method, decision calculation ofservice scheduling is carried out on a user service request by taking a service quality guarantee of user mobile handover as a target, and an optimization scheme of service deployment and migration is generated, wherein the service deployment and migration scheme is expressed as a deployment matrix; performing iterative optimization on a plurality of pre-defined deployment matrixes by decision calculation; wherein the optimization target comprises signal propagation delay from a user to a service, a resource occupancy rate and migration time of the service, and the optimization step comprisesmatrix scoring, weighted random selection and reconstruction according to scores, inter-matrix row crossing and single matrix element displacement, and performing constraint test on a result, whereinthe completion condition of the decision calculation is that the number of iterations reaches a preset value, or the number of continuous iterations which do not meet the constraint reaches a presetvalue. The invention provides an efficient service scheduling method for user handover of mobile edge calculation.