222results about How to "Reduce the effective area" patented technology

The invention belongs to the technical fields of semiconductors, and particularly relates to an enhancement mode HEMT (high electron mobility transistor) device. According to the enhancement mode HEMT device, a reverse polarization layer is grown on the upper surface of a barrier layer between a grid electrode and a drain electrode; the reverse polarization layer and the barrier layer produce reverse polarization to form two-dimensional hole gas (2DHG) in heterojunction interface; the reverse polarization layer, barrier layer, buffering layer form polarization super junctions; meanwhile, a metal grid electrode is not positioned between a source electrode and the drain electrode any more, instead, an insulation gate electrode is formed by etching a groove in the edge of the source edge far from the drain electrode; on one hand, longitudinal conductive channels between the source electrode and two-dimensional electron gas (2DEG) are cut by the 2DHG; the magnetic field control on the conductive channels is realized by applying voltage on the groove gate electrode so as to realize the enhancement mode; and the regulation and control on the threshold value voltage can be realized by doping parts of the conductive channels; and on the other hand, the polarization super junctions between the gate electrode and the drain electrode assist to use up a drifting region in a blocked state so as to optimize the transverse electric field distribution of the device and improve the voltage resistance of the device.

A method for increasing resolution of a focal plane array having a plurality of pixels dispersed across a total pixel area is described. The method includes providing an active pixel area for the focal plane array that is less than the total pixel area, acquiring image data utilizing the reduced active pixel area, and storing the image data in a portion of a memory, the memory having a capacity corresponding to the total pixel area of the focal plane array.

A method for designing a semiconductor integrated circuit is provided that is capable of a timing simulation that is approximate to an actual operation by reducing the effect of IR drop on the timing without reducing an effective area necessary for arrangement of elements or the number of pads that can be used other than power supply pads and without increasing the processing time. In a FF driving ability change procedure, a flip-flop having a delay time larger than a transition time from a state in which an IR drop occurs in a power supply voltage to a state of an ideal power supply voltage is substituted for an arbitrary flip-flop. Thus, a delay library considering IR drop may be produced previously only for the flop-flop, thus enabling a production time of the library to be reduced and improving the calculation accuracy of the delay time in the delay calculation procedure. Furthermore, the substitution of a flip-flop having a low driving ability enables the area to be reduced.