Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. An insulating ring penetrating through a substrate is formed in the substrate, and the substrate in the insulating ring serves as a first polar plate of a capacitor structure; a through hole is formed in the first polar plate, and a dielectric layer is formed on the side wall of the through hole and conducting layersare filled in the through hole; the first polar plate is led out through a leading-out structure, all conducting layers are electrically connected through a second leading-out structure and are led out, and second polar plates, connected in parallel via all conducting layers, of the capacitor structure are formed; the dielectric layer in the through hole is an insulating layer between polar plates of two capacitor structures, and the connection and use of the capacitor structures can be realized through the leading-out structures. The capacitor structures have a larger capacity, and meanwhile, the conducting layers in the through hole are connected in parallel through the leading-out structures to realize the capacitors of any required capacity, and the semiconductor device has better expandability, so that a capacitor structure with larger capacity can be formed on a smaller chip area, and the integration level of a chip is effectively improved.

Description

technical field [0001] The invention relates to the field of semiconductor devices and their manufacture, in particular to a semiconductor device and its manufacturing method. Background technique [0002] With the continuous development of semiconductor technology, the integration level of integrated circuits has also been continuously improved. In the chip design of integrated circuits, active devices and passive devices are usually integrated at the same time. Passive devices such as resistors and capacitors also occupy the area of ​​the chip, especially in the chip design of 3D NAND memory. The peripheral circuit consists of HVMOS (High Voltage Metal Oxide Semiconductor, High Voltage Metal Oxide Semiconductor) device and LVMOS (Low Voltage Metal Oxide Semiconductor, Low Voltage Metal Oxide Semiconductor) device, the peripheral circuit is used to operate the storage unit, and the operation of the 3D NAND storage unit is High voltage, so a large number of capacitors are n...

AI Technical Summary

Problems solved by technology

In the chip design of integrated circuits, active devices and passive devices are usually integrated at the same time. Passive devices such as resistors and capacitors also occupy the area of ​​the chip, especially in the chip design of 3D NAND memory. The peripheral circuit consists of HVMOS (High Voltage Metal Oxide Semiconductor, High Voltage Metal Oxide Semiconductor) device and LVMOS (Low Voltage Metal Oxide Semiconduc...

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