Vertical channel fin field-effect transistors having increased source/drain contact area and methods for fabricating the same

a technology of vertical channel fins and field-effect transistors, which is applied in the field of field-effect transistors, can solve problems such as problems such as problems, deterioration of the gate control channel capacity, and problems such as operation and structural problems

Inactive Publication Date: 2005-08-25
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0013] According to further embodiments of the present invention a method of forming a fin field-effect transistor may include forming a fin-shaped active region having first and second source/drain regions therein and a channel region therebetween vertically protruding from a semiconductor substra...

Problems solved by technology

As semiconductor devices are scaled-down, a variety of operational and structural problems may result.
For example, in field-effect transistors (FETs) having a planar channel region, problems may occur when the length of the channel region is reduced to 100 nm and below.
Since an electric fiel...

Method used

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  • Vertical channel fin field-effect transistors having increased source/drain contact area and methods for fabricating the same
  • Vertical channel fin field-effect transistors having increased source/drain contact area and methods for fabricating the same
  • Vertical channel fin field-effect transistors having increased source/drain contact area and methods for fabricating the same

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Embodiment Construction

[0087] The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. However, this invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout.

[0088] It will be understood that when an element such as a layer, region or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. It will also ...

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Abstract

A fin field-effect transistor (FinFET) device includes a fin-shaped active region having first and second source/drain regions therein and a channel region therebetween vertically protruding from a semiconductor substrate. A gate electrode is formed on an upper surface and sidewalls of the channel region. First and second source/drain contacts are formed on respective upper surfaces and sidewalls of the first and second source/drain regions of the fin-shaped active region at opposite sides of the gate electrode. The channel region may be narrower than the first and second source/drain regions of the fin-shaped active region.

Description

CLAIM OF PRIORITY [0001] The present application claims priority from Korean Patent Application No. 10-2004-0012371 filed on Feb. 24, 2004, the disclosure of which is hereby incorporated by reference herein in its entirety. FIELD OF THE INVENTION [0002] The present invention relates to semiconductor devices, and more particularly, to field-effect transistors and methods for fabricating the same. BACKGROUND OF THE INVENTION [0003] As semiconductor devices are scaled-down, a variety of operational and structural problems may result. For example, in field-effect transistors (FETs) having a planar channel region, problems may occur when the length of the channel region is reduced to 100 nm and below. More particularly, planar channel FETs may include gate electrodes that are formed on a planar channel region. Since an electric field at upper and lower portions of the channel may be asymmetrical, the capacity of the gate to control the channel may become deteriorated as channel length is...

Claims

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Application Information

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IPC IPC(8): H01L21/336H01L29/76H01L29/786H01L29/94H01L31/062H01L31/113
CPCH01L29/66818H01L29/78618H01L29/785E02D29/0241E02D29/025E02D29/0266E02D2600/20E02D2600/40
Inventor OH, CHANG-WOOPARK, DONG-GUNLEE, SUNG-YOUNGCHOE, JEONG-DONGKIM, DONG-WON
Owner SAMSUNG ELECTRONICS CO LTD
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