Vertical channel fin field-effect transistors having increased source/drain contact area and methods for fabricating the same

Abstract

A fin field-effect transistor (FinFET) device includes a fin-shaped active region having first and second source / drain regions therein and a channel region therebetween vertically protruding from a semiconductor substrate. A gate electrode is formed on an upper surface and sidewalls of the channel region. First and second source / drain contacts are formed on respective upper surfaces and sidewalls of the first and second source / drain regions of the fin-shaped active region at opposite sides of the gate electrode. The channel region may be narrower than the first and second source / drain regions of the fin-shaped active region.

Description

CLAIM OF PRIORITY [0001] The present application claims priority from Korean Patent Application No. 10-2004-0012371 filed on Feb. 24, 2004, the disclosure of which is hereby incorporated by reference herein in its entirety. FIELD OF THE INVENTION [0002] The present invention relates to semiconductor devices, and more particularly, to field-effect transistors and methods for fabricating the same. BACKGROUND OF THE INVENTION [0003] As semiconductor devices are scaled-down, a variety of operational and structural problems may result. For example, in field-effect transistors (FETs) having a planar channel region, problems may occur when the length of the channel region is reduced to 100 nm and below. More particularly, planar channel FETs may include gate electrodes that are formed on a planar channel region. Since an electric field at upper and lower portions of the channel may be asymmetrical, the capacity of the gate to control the channel may become deteriorated as channel length is...

AI Technical Summary

Benefits of technology

[0013] According to further embodiments of the present invention a method of forming a fin field-effect transistor may include forming a fin-shaped active region having first and second source/drain regions therein and a channel region therebetween vertically protruding from a semiconductor substra...

Problems solved by technology

As semiconductor devices are scaled-down, a variety of operational and structural problems may result.

For example, in field-effect transistors (FETs) having a planar channel region, problems may occur when the length of the channel region is reduced to 100 nm and below.

Since an electric field at upper and lower portions of the channel may be asymmetrical, the capacity of the gate to control the channel may become deteriorated as channel length is decreased.

However, in some instances, the shape of the fin may be altered due to over-etching of the fin when the gate electrode is formed.

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