Method of forming a transistor having multiple channels

Abstract

A transistor (10) overlies a substrate (12) and has a plurality of overlying channels (72, 74, 76) that are formed in a stacked arrangement. A continuous gate (60) material surrounds each of the channels. Each of the channels is coupled to source and drain electrodes (S / D) to provide increased channel surface area in a same area that a single channel structure is conventionally implemented. A vertical channel dimension between two regions of the gate (60) are controlled by a growth process as opposed to lithographical or spacer formation techniques. The gate is adjacent all sides of the multiple overlying channels. Each channel is formed by growth from a common seed layer and the source and drain electrodes and the channels are formed of a substantially homogenous crystal lattice.

Description

RELATED APPLICATION[0001]This application is related to U.S. patent application Ser. No. 10 / 074,732, entitled “Method of Forming A Vertical Double Gate Semiconductor Device And Structure Thereof” filed Feb. 13, 2002, and assigned to the assignee hereof.FIELD OF THE INVENTION[0002]This invention relates generally to semiconductors, and more specifically, to the manufacture of and the structure of semiconductor devices.BACKGROUND OF THE INVENTION[0003]As semiconductor devices continue to become smaller in size, the devices must be what is known in the industry as “scalable”. That is, the devices must continue to be able to be made with reduced dimensions and still function at the required specifications. Traditionally, MOSFETs have been implemented with a single control electrode or gate on a planar substrate. The gate is placed between a source and drain electrode and functioned to create a channel for controlling the amount of current conducted by the MOSFET. Because there is a gate...

AI Technical Summary

Benefits of technology

The present invention relates to a method of manufacturing a semiconductor device with a vertical double gate structure. This structure allows for improved scalability and better control of leakage current. The invention also includes a method of forming a plurality of overlying channels in a semiconductor device. The invention provides a semiconductor device with a thinner silicon fin, which allows for better short channel control. The invention also includes a method of patterning the semiconductor device and removing a portion of the layers. The technical effects of the invention include improved scalability, better leakage control, and improved performance of the semiconductor device.

Problems solved by technology

Single control of the channel leads to undesired leakage current (i.e. electron or hole flow) between the source and drain when the transistor is intended to be non-conductive.

For example, known planar MOSFETs and FINFETs having multiple channels are formed laterally and thus require significant additional area.

However, lithographically or spacer defined dimensions do not offer as much manufacturing control as grown layers to form a transistor channel.

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