Semiconductor integrated circuit device and production method thereof
a technology of integrated circuit device and semiconductor substrate, which is applied in the direction of semiconductor devices, electrical devices, transistors, etc., can solve the problems of reducing the refresh characteristic of the semiconductor substrate, the variation of the threshold voltage, etc., and achieves the reduction of the leakage current between the storage node and the semiconductor substrate, the effect of improving the refresh characteristi
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first embodiment
[0068] Hereinafter, embodiments of the present invention will be described in detail based on the drawings.
[0069]FIG. 1 is a cross-sectional view showing the principal part of a semiconductor integrated circuit device according to a first embodiment of the present invention. FIGS. 2 to 32 are cross-sectional views and plan views showing the principal part of the semiconductor integrated circuit device of FIG. 1 during the production process thereof.
[0070] First, the sectional structure of a semiconductor integrated circuit device according to the first embodiment will be described with reference to FIG. 1.
[0071] A semiconductor substrate 1 is made of, for example, a single crystal silicon whose a conductivity type is a p type. This semiconductor substrate 1 has a memory cell area and logic circuit areas (peripheral circuit area), and the central portion of FIG. 1 illustrates the memory cell area and the left side of the memory cell area illustrates a first logic circuit area and ...
second embodiment
[0243] This embodiment relates to a production process for the source and drain (semiconductor area) in the logic circuit area. In the first embodiment, to simplify the process, the high concentration semiconductor area is formed after the (low concentration) semiconductor area is formed in the first and second logic circuit areas.
[0244] In contrast, in this second embodiment, the low concentration semiconductor area is formed after the high concentration semiconductor area is formed in the logic circuit area.
[0245] Since the production method until the process of dry-etching the gate electrode in this embodiment is the same as that in the first embodiment described with reference to FIGS. 2 to 12, the descriptions thereof will be omitted.
[0246] First, the semiconductor substrate 1 shown in FIG. 12 described in the first embodiment is prepared, and impurities are implanted with using the gate electrode and a resist film (not shown) as masks, and thereby the semiconductor areas 5a...
third embodiment
[0259] A third embodiment relates to the formation of the contact electrodes in the memory cell area. In the first embodiment, the high-concentration semiconductor area in the logic circuit area is formed after the polycrystalline silicon film 24 is formed, and further the polycrystalline silicon film 24c is removed. The removal of the polycrystalline silicon film 24c is performed to further ion-implant an n type impurity such as phosphorus into the semiconductor areas 5a and 5b and form the contact electrodes (12a and 12b) on the semiconductor areas 5a and 5b.
[0260] In contrast, in this embodiment, the n type polycrystalline silicon film is deposited on the semiconductor substrate after the source and drain (semiconductor areas) of the memory cell selecting MISFET Q are exposed.
[0261] Since the production process until the step of forming the silicon oxide film 7 in this embodiment is the same as that in the first embodiment described with reference to FIGS. 2 to 14, the descript...
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