30results about How to "Reduce GIDL" patented technology

An SOI substrate, a semiconductor device, and a method of backgate work function tuning. The substrate and the device have a plurality of metal backgate regions wherein at least two regions have different work functions. The method includes forming a mask on a substrate and implanting a metal backgate interposed between a buried oxide and bulk regions of the substrate thereby producing at least two metal backgate regions having different doses of impurity and different work functions. The work function regions can be aligned such that each transistor has different threshold voltage. When a top gate electrode serves as the mask, a metal backgate with a first work function under the channel region and a second work function under the source/drain regions is formed. The implant can be tilted to shift the work function regions relative to the mask.

To provide a semiconductor device using a Fin-FET and having a contact configuration such that the GIDL is reduced while limiting an increase in contact resistance, source and drain regions of the Fin-FET are formed by solid-phase diffusion positively utilizing impurity implantation after forming of contact holes 13 and oozing-out of an impurity from polysilicon contact plugs 14. Also, contact plugs 14 are extended to side surfaces of convex semiconductor layers 101a to form side wall portions 14a, thereby increasing the contact area.

A row driver circuit is disclosed for supplying a reset voltage to a plurality of reset transistors of an active pixel sensor array while minimizing gate induced drain leakage (GIDL). The row driver circuit is configured to supply a high voltage level (e.g., Vdd or higher) to the reset transistors of the array during a reset operation. The row driver circuit is further configured to supply a low voltage level (e.g., a voltage level higher than ground) to the reset transistors of the array when the pixels are not being reset (e.g., during integration). The reduced potential difference realized between the respective gates of the reset transistors and the respective photodiodes of the pixels, when the pixels are not being reset, results in reduced GIDL.

The invention provides a thin film transistor, an active matrix organic light emitting diode assembly and a manufacturing method of the thin film transistor and the active matrix organic light emitting diode assembly. The thin film transistor comprises a substrate, a buffering layer, a semiconductor layer, a first gate insulating layer, a second gate insulating layer foot and a gate electrode; wherein the buffering layer is located on the substrate; the semiconductor layer is located on the buffering layer and comprises a source region, a drain region and a channel region; the first gate insulating layer covers the semiconductor layer; the second gate insulating layer foot is located on the first gate insulating layer, and the width of the second gate insulating layer foot is smaller than that of the first gate insulating layer; the gate electrode is located on the second gate insulating layer foot. The part, located on the semiconductor layer, of the first gate insulating layer is provided with a flat upper surface.

A semiconductor device having a buried gate that can realize a reduction in gate-induced drain leakage is presented. The semiconductor device includes a semiconductor substrate, a buried gate, and a barrier layer. The semiconductor substrate has a groove. The buried gate is formed in a lower portion of the groove and has a lower portion wider than an upper portion. The barrier layer is formed on sidewalls of the upper portion of the buried gate.

A semiconductor device with a gate having a bulbous area and a flattened area underneath the bulbous are is presented. The semiconductor device includes a semiconductor substrate, an isolation layer, a gate insulation layer, and gates. The semiconductor substrate has recess parts that have first grooves which have bulbous-shaped profiles and second vertically flattened profile grooves which extend downward from the first grooves. The gates are formed in the recess parts in which the gate insulation layer is double layered in the bulbous profile areas and is single layered in the flattened profile areas.

A semiconductor device and a method for manufacturing the same are disclosed. A recess gate structure is formed between an overlapping region between a gate and a source/drain so as to suppress increase in gate induced drain leakage (GIDL), and a gate insulation film is more thickly deposited in a region having weak GIDL, thereby reducing GIDL and thus improving refresh characteristics due to leakage current.

The invention relates to a semiconductor structure and a preparation method thereof. The preparation method of the semiconductor structure comprises the steps of providing a substrate; forming a groove in the substrate, wherein the bottom and the side wall of the groove are covered by the dielectric layer; forming a sacrificial layer in the dielectric layer; forming a conductive layer, wherein the upper surface of the conductive layer is lower than the upper surface of the substrate; removing the sacrificial layer to form air side walls on two opposite sides of the conductive layer; and forming an insulation protection layer, wherein the insulation protection layer covers the upper surface of the conductive layer and the top of the air side wall. According to the preparation method of the semiconductor structure, the conductive layer with relatively high height is formed in the groove, and the cross sectional area of the conductive layer can be increased under the condition that the line width of the word line structure is kept unchanged, so that the word line resistance is greatly reduced, the word line conduction current is improved, and the response speed of a transistor is improved; in addition, the air side walls are formed on the two opposite sides of the conducting layer, so that the electric field between the grid electrode and the drain electrode can be reduced, the GIDL is reduced, the crystal power consumption of the transistor is reduced, and the reliability of the transistor is improved.

The invention discloses a semiconductor device, a manufacturing method thereof and electronic equipment comprising the semiconductor device. According to an embodiment, a semiconductor device may include: an active region extending substantially in a vertical direction on a substrate; the grid stack is formed around at least part of the periphery of the middle section, in the vertical direction, of the active region, and the active region comprises a channel region opposite to the grid stack, and a first source/drain region and a second source/drain region which are arranged on the two opposite sides, in the vertical direction, of the channel region respectively; the gate stack comprises a gate dielectric layer, a work function adjusting layer and a gate electrode material layer, and the work function adjusting layer is arranged between the gate electrode material layer and the channel region; and the first low-k dielectric layer extends from the first end of the work function adjusting layer to surround a first corner of the end part, close to one side of the channel region, of the gate electrode material layer.