Method for forming semiconductor device with metal grid electrode

Abstract

The invention provides a method for forming a semiconductor device with a metal grid electrode, which comprises the steps of: providing a front-end device structure, wherein the front-end device structure is provided with a semiconductor substrate and an interlayer medium layer arranged on the semiconductor substrate, the interlayer medium layer is internally provided with an opening from which a part of the semiconductor substrate is exposed, and the semiconductor substrate which is arranged at two sides of the opening and is covered by the interlayer medium layer is internally provided with a source electrode / a drain electrode; forming a barrier layer on the front-end device structure; etching the barrier layer, so that a barrier gap wall layer is formed on the side wall of the opening; performing an ion implantation technology to the semiconductor substrate by the means that the barrier gap wall layer and the interlayer medium layer are taken as mask films, so that an unevenly-doped channel is formed; removing the barrier gap wall layer; and forming a high-k material layer in the opening, and filling with metal, so that the semiconductor device with the metal grid electrode is formed. After the semiconductor device with the metal grid electrode is formed according to the method provided by the invention, not only can the gate induced drain leakage (GIDL) be effectively reduced, but also the short channel effect can be improved.

Description

Technical field [0001] The present invention relates to a semiconductor manufacturing process, in particular to a method of forming a semiconductor device with a metal gate. Background technique [0002] With the rapid development of microelectronics technology, CMOS technology, the core of microelectronics technology, has become the supporting technology in modern electronic products. For decades, chip manufacturers have consistently adopted silicon dioxide (SiO 2 ) As the gate dielectric layer and using doped polysilicon as the gate electrode material. This combination continues until the 90-nanometer node era. As the critical size (CD) continues to shrink, the SiO in CMOS transistors 2 The size of the gate dielectric layer has reached its limit. For example, when using the 65nm node process, SiO 2 The height of the gate dielectric layer has been reduced to 1.2 nanometers, which is about the height of 5 silicon atomic layers. If it is further reduced, the leakage current and ...

AI Technical Summary

Problems solved by technology

[0007] However, semiconductor devices with metal gates formed by this traditional method have high gate-induced leakage current (GIDL), which affects the reliability of semiconductor devices and reduces their overall performance

The traditional solution to the problem of excessively high GIDL is to reduce the concentration of channel doping, but this will aggravate the problem of short channel effect

Images