Method and device to reduce gate-induced drain leakage (GIDL) current in thin gate oxide MOSFETs

Abstract

A process for the fabrication of an integrated circuit which provides a FET device having reduced GIDL current is described. A semiconductor substrate is provided wherein active regions are separated by an isolation region, and a gate oxide layer is form on the active regions. Gate electrodes are formed upon the gate oxide layer in the active regions. An angled, high dose, ion implant is performed to selectively dope the gate oxide layer beneath an edge of each gate electrode in a gate-drain overlap region, and the fabrication of the integrated circuit is completed.

Description

CROSS REFERENCE TO RELATED APPLICATIONS [0001] This application is a continuation of U.S. patent application Ser. No. 09 / 648,044 filed Aug. 25, 2000.TECHNICAL FIELD [0002] The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of reducing Gate Induced Drain Leakage (GIDL) current by selectively increasing electrical gate oxide thickness only in the gate / drain overlap region during the fabrication of integrated circuits. BACKGROUND OF THE INVENTION [0003] In the fabrication of integrated circuits, as the sizes of semiconductor devices, such as state-of-the-art Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), are scaled down, performance issues regarding the current driving capabilities of these devices exist. Since the current driving capability is a function of both source resistance and gate oxide thickness, better performance in these devices is achievable through thinner gate oxide and spacer layers. However, it has...

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Benefits of technology

[0008] The method of the present invention employs a non-orthogonal ion implant process by which the gate-oxide layer in the gate-drain overlap region of a FET device is selectively doped with fluorine or chlorine ions. The dosage of the ion implant is such that the ion concentration increases the ‘electrical’ gate oxide thickness near the gate-source / drain corners, thereby lowering the dielectric constant of the gate-oxide layer in the gate-drain overlap region without actual thickness growth to the ion doped gate-oxide layer. Since GIDL is exponentially dependent on the magnitude of the surface electrical field, even a slight reduction in the electrical field results in a dramatic reduction in GIDL. Accordingly, supplementing existing FET fabrication processes with the method of the preset invention, lowers the effective surface electrical field in the overlap region, and thereby minimizes GIDL in FET devices wherein the present invention is practiced.

[0010] In accordance with one aspect of the present invention, provided is a circuit structure comprising a semiconductor layer; an oxide layer formed on the semiconductor layer; a polysilicon layer formed on the oxide layer; a gate structure formed from the polysilicon layer, the gate structure having a defined leading edge; and an overlap region beneath the gate structure and adjacent the leading edge having a predetermined ion implant concentration, the predetermined implant concentration is sufficient to increase the electrical gate oxide thickness in the overlap region.

[0011] In accordance with another aspect of the present invention, provided is a method for fabricating a structure on a semiconductor layer comprising the steps of forming an oxide layer on a semiconductor layer; forming a polysilicon layer on the oxide layer; patterning the polysilicon layer into a gate structure having a defined leading edge, and to expose the oxide layer; and implanting ions into the oxide layer at an overlap region beneath the gate structure and adjacent the defined leading edge to a predetermined ion implant concentration which is sufficient to increase the electrical gate oxide thickness only in the overlap region without thickness growth of the oxide layer, the ions being implanted at a tilt angle non-orthogonal to the plane of the semiconductor layer.

[0012] In accordance with still another aspect of the present invention, provided is a method of reducing Gate Induced Drain Leakage (GIDL) current within Field Effect Transistors (FETs) comprising the steps of: forming on a semiconductor substrate a field effect transistor structure comprising a gate oxide layer, a gate electrode on the gate oxide layer and two source / drain regions formed within the semiconductor substrate; annealing the semiconductor substrate; implanting ions into the gate oxide layer beneath the gate electrode and adjacent the drain region, which defines an overlap region, to a predetermined ion implant concentration which is sufficient to increase electrical gate oxide thickness only in the overlap region, the ions being implanted at a tilt angle non-orthogonal to the plane of the semiconductor substrate; and completing the fabrication of the semiconductor substrate.

[0013] An object of the present invention is to provide a method of reducing gate induced drain leakage current by selectively increasing the electrical gate oxide thickness only in the gate / drain overlap region during the fabrication of integrated circuits.

[0014] Another object of the invention is to provide a manufacturable method for fabricating integrated circuits which will result in reduced gate induced drain leakage.

Problems solved by technology

In the fabrication of integrated circuits, as the sizes of semiconductor devices, such as state-of-the-art Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), are scaled down, performance issues regarding the current driving capabilities of these devices exist.

However, it has been observed that as the gate oxide is made thinner, gate-induced drain leakage (GIDL) currents degrade the performance of these devices as the GIDL currents become a larger percentage of the total sub-threshold leakage current.

Unfortunately, it has been observed that by increasing the doping density in the channel and source / drain regions, the surface electric field also increases, resulting in more band bending and hence, even more GIDL current.

Thus, difficulties exist in providing a scaled down semiconductor device having a suitable balance between high current driving capability and low GIDL current.

However, having a thick gate oxide in the gate-source region increases source resistance, which in turn, reduces the current driving capability of the device.

However, having an increased material thickness of the oxide layer in the gate-drain region hampers current drives of the transistor and also cause increased stress in the active area near the overlap region due to volume expansion.

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