IGBT device, preparation method and preparation system thereof, and storage medium

Abstract

The invention discloses an IGBT device, a preparation method and a preparation system thereof, and a storage medium. The device comprises a substrate; the second groove region and the first groove region are formed in the substrate; the semi-insulating material layer is formed in the first groove region and the second groove region; a CS layer, a Pwell layer and an NSD layer; a contact hole penetrating from top to bottom; the contact hole is filled with a metal contact layer. According to the invention, the first groove region and the second groove region are formed on the side wall of the first HM layer, gate oxidation, polysilicon filling and the second HM layer are carried out in sequence, ion implantation and annealing are carried out, and the gate oxide layer between the grooves is used as a barrier mask to realize etching of the contact hole. The method is suitable for forming the contact hole under the condition that the cellular mesa is small, photoetching sleeve deviation between the contact hole and the groove can be effectively avoided, so that the in-chip consistency of saturation voltage drop is greatly improved, and meanwhile, a wider upper opening can be formed so as to be beneficial to further reducing the conduction voltage drop of a device.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device and a preparation method, a preparation system and a storage medium thereof, in particular to an IGBT device and a preparation method, a preparation system and a storage medium thereof. BACKGROUND

[0002] In modern high-power wind power, photovoltaic inverter and energy storage converter applications, as an important component of switching, IGBT is often used in multi-chip parallel mode, and the consistency of saturation voltage drop affects the long-time stable operation of the module.

[0003] To solve the problem of saturation voltage drop consistency in the chip, especially when the pitch is reduced to 1.6um or less, the industry often starts from improving the contact hole and trench overlay accuracy, and reduces the overlay through optical angle, but the effect is very small. SUMMARY

[0004] The purpose of the present application is to provide an IGBT device which can avoid the overlay between the contact hole and the trench, thereby greatly improving the saturation voltage drop consistency in the chip;

[0005] The second purpose of the present application is to provide a preparation method of the above-mentioned IGBT device;

[0006] The third purpose of the present application is to provide a preparation system of the above-mentioned IGBT device;

[0007] The fourth purpose of the present application is to provide a computer-readable storage medium.

[0008] Technical scheme: the IGBT device provided by the present application comprises:

[0009] a semiconductor substrate;

[0010] a plurality of first trench regions arranged at intervals formed in the semiconductor substrate, and a second trench region located above the first trench region and connected with the first trench region; the etching angle of the second trench region is greater than the etching angle of the first trench region and both are acute angles;

[0011] a gate oxide layer formed on the surface of the first and second trench regions;

[0012] a semi-insulating material layer grown in the first and second trench regions for connecting the gate potential;

[0013] an ion implantation layer formed between each interval arranged trench region, which is CS layer, Pwell layer and NSD layer from bottom to top;

[0014] a contact hole penetrating and connecting the NSD layer and the Pwell layer from top to bottom;

[0015] The contact hole is filled with a metal contact layer.

[0016] Wherein, the CS layer refers to a N-type semiconductor region formed by phosphorus ion implantation, the Pwell layer refers to a P-type semiconductor region formed by boron ion implantation, and the NSD refers to a N-type semiconductor region formed by arsenic ion implantation; in the present application, the layers are formed in sequence by phosphorus ion implantation, boron ion implantation and arsenic ion implantation.

[0017] Wherein, the etching angle for forming the first trench region is 80-90°, and the trench depth is 3-5um; the etching angle for forming the second trench region is 70-80°, and the trench depth is 1-3um.

[0018] Wherein, the etching angle of the contact hole is 70-90°, and the depth is 0.3-0.6um.

[0019] Wherein, after the first trench region and the second trench region are formed and after gate oxidation is performed, the semi-insulating material is filled once, and the depth of the semi-insulating material layer in the second trench is 1-3um, which is the same as the depth of the second trench. After the semi-insulating material is filled, back etching is performed to a position 0.1-0.4um below the top of the second trench, and a shape of two sides high and middle low with a middle inward recess is formed. Preferably, the semi-insulating material is polysilicon.

[0020] The preparation method of the IGBT device, comprising the following steps:

[0021] (A) depositing a plurality of first HM layers on the semiconductor substrate with intervals;

[0022] (B) forming side walls on both sides of the first HM layer;

[0023] (C) etching downward in the semiconductor substrate region between adjacent first HM layers to form a first trench region;

[0024] (D) removing the side walls on both sides of the first HM layer, and etching a second trench region above the first trench region;

[0025] (E) forming a gate oxide layer on the inner surfaces of the first trench region and the second trench region, and then depositing a semi-insulating material layer into the first trench region and the second trench region, and performing back etching;

[0026] (F) depositing a second HM layer on the structure obtained in step (E);

[0027] (G) performing CMP to the surface of the semiconductor substrate to form an ion implantation region;

[0028] (H) performing ion implantation to form a CS layer, a Pwell layer and an NSD layer in sequence from bottom to top.

[0029] (I) using the gate oxide layer between the trench regions arranged at intervals as a mask layer, etching a contact via hole;

[0030] (J) completing front metalization.

[0031] In the present application, "HM" refers to a hard mask.

[0032] The etching angle of the first trench region is 80-90°, and the trench depth is 3-5um; the etching angle of the second trench region is 70-80°, and the trench depth is 1-3um.

[0033] The thickness of the first HM layer is 0.5-1um; the lateral spacing of adjacent first HM layers is 0.6-0.8um; the thickness of the second HM layer is 0.5-1um.

[0034] In step (E), after the etching back, a shape of two sides high and middle low with the middle inwardly recessed is formed, and the etching back is performed to a position below the top of the second trench region by 0.1-0.4um.

[0035] In step (H), the implantation doses of the CS layer, the Pwell layer and the NSD layer are 1e12-3e13cm -3 , 1e13-3e13cm -3 , 1e15-3e15cm -3 , respectively, and the annealing conditions are 1150-1250℃, 100-300min; 1100-1150℃, 100-300min; 850-950℃, 30-60min, respectively.

[0036] The preparation system of the IGBT device described above comprises the following modules:

[0037] A substrate module is used to provide a semiconductor substrate.

[0038] A first deposition module is used to deposit a first HM layer and form a side wall on the side of the first HM layer.

[0039] A trench module is used to form a second trench region and a first trench region from the top of the semiconductor substrate in sequence.

[0040] A second deposition module is used to form a gate oxide layer on the inner surface of the first trench region and the second trench region, deposit a semi-insulating material layer into the two trench regions, perform etching back, and deposit a second HM layer.

[0041] A CMP module is used to perform CMP to form an ion implantation region.

[0042] Self-alignment module: used for self-alignment etching contact hole and front metal.

[0043] A computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the method of any one of the above.

[0044] Invention principle: the prior art can only ensure steep angle in the process of etching trench, and the typical angle is 89°, and the relatively wide top cannot be etched further, and the present application forms two-stage trench area and keeps the top trench area larger, thereby reducing the MESA size of the cell, and the carrier concentration around the trench is further enhanced, so that the on-state voltage drop can be reduced.

[0045] Beneficial effects: compared with the prior art, the present application has the following remarkable effects:

[0046] (1) the present application forms two-stage trench area by controlling the etching angle, so that the etching angle of the first trench area is greater than that of the second trench area, thereby forming a wider upper opening, so that the on-state voltage drop can be reduced by 0.1-0.2V; (2) based on the semiconductor substrate, the present application forms side walls on the side edges of the spaced HM layer, and then forms the first and second trench areas, and then fills the semi-insulating material and the second HM, and then performs ion implantation and annealing, and uses the gate oxide layer between the spaced trenches as a barrier mask to realize the etching of the contact hole, the present application is suitable for the formation of contact hole under the condition that the cell mesa is small, and can effectively avoid the photolithography offset between the contact hole and the trench without affecting the photolithography precision, thereby greatly improving the on-chip consistency of the saturation voltage drop, and the process is simple and reliable, and the realization difficulty is low. BRIEF DESCRIPTION OF DRAWINGS

[0047] Figure 1 The flow chart of the preparation method of the IGBT device of the present application is shown in the figure.

[0048] Figures 2 to 11 The structure schematic diagram obtained by sequentially corresponding to each step in steps (1) to (10) in example 1. DETAILED DESCRIPTION

[0049] The present application will be further described in detail below.

[0050] Example 1

[0051] A preparation method of an IGBT device, the flow chart is shown in the figure Figure 1 , and specifically includes the following steps:

[0052] (1) An FZ silicon wafer with a substrate resistivity of 30 Ωcm is used as the N-type semiconductor substrate. Hidden matrix (HM) layers are deposited on the substrate. After photolithography using a trench mask and removal of the resist, several uniformly spaced first HM layers are formed. The HM can be silicon dioxide or an insulating material such as silicon nitride; in this embodiment, silicon dioxide is used. The thickness of each first HM layer is 0.6 μm, and the lateral spacing between adjacent first HM layers is 0.7 μm. The resulting structure is as follows: Figure 2 As shown;

[0053] (2) A 0.9 μm thick polysilicon layer is deposited on the structure formed in step (1) and etched to form polysilicon sidewalls on both sides of each first HM, resulting in the structure shown below. Figure 3 As shown;

[0054] (3) Next, at an etching angle of 89°, etching is performed downwards along the outer side of the polysilicon sidewall and the interface with the substrate, with the etching depth controlled to be 4.5 μm, forming the first trench region, the structure of which is as follows. Figure 4 As shown;

[0055] (4) After forming the first trench region in step (3), the polysilicon sidewalls on both sides of each first HM layer are removed, and at a specific angle of 80°, the exposed side of the first HM is etched downwards at the junction with the substrate until it connects with the first trench region, thereby forming a second trench region in the area between the first trench region and the first HM layer, as shown in the structure. Figure 5 As shown, the connecting area between the two trench regions is further rounded to reduce the electric field within the trench;

[0056] (5) Remove the remaining first HM layer on the substrate surface, and then perform gate oxidation on the inner surfaces of the first and second trench regions, so that a gate oxide layer with a thickness of about 0.12 μm is grown on the inner surfaces of the two trench regions. The inner surface includes two sides and a bottom edge, and the gate oxide layer material is silicon dioxide. Next, fill the two trench regions with polysilicon and perform back etching, so that the top of the polysilicon in the second trench region forms a shape with the middle recessed inward, the sides higher and the middle lower. The lowest point of the top of the polysilicon layer is 0.2 μm lower than the top of the substrate, as shown in the structure. Figure 6 As shown;

[0057] (6) Deposit HM onto the structure obtained in step (5) until it protrudes above the substrate surface to obtain a second HM layer, and then etch back to form a shape where the top of the second HM layer is also concave in the middle, with high sides and low center. The thickness of the second HM layer is 0.7 μm, and the structure is as follows: Figure 7 As shown;

[0058] (7) Next, CMP is performed on the structure obtained in step (6) to grind it to the substrate surface, such as... Figure 8 As shown;

[0059] (8) to the interval between the trench region, in turn, phosphorus ion implantation, boron ion implantation, arsenic ion implantation and annealing, so as to form CS layer, Pwell layer and NSD layer in turn; wherein the implantation dose is 8e12cm -3 , 2e13cm -3 , 3e15cm -3 , annealing conditions are 1150℃ 150min, 1150℃ 150min, 950℃ 60min; form as Figure 9 indicated structure;

[0060] (9) using the gate oxide layer between each interval between the trench as a mask layer, etching contact via, as shown in Figure 10 ;

[0061] (10) complete the front metal, the front metal is 5um thickness of AlCu, front metal process for prior art, form as Figure 11 indicated final structure.

[0062] The embodiment can realize that the opening size of the trench top is 0.88um, and the test saturation pressure drop is 1.87V.

[0063] The preparation system of the IGBT device, comprising the following modules:

[0064] Substrate module: for providing a semiconductor substrate;

[0065] Primary deposition module: for depositing a first HM layer and forming a side wall on the side of the first HM layer;

[0066] Trench module: for forming a second trench region and a first trench region from the top of the semiconductor substrate in turn;

[0067] Secondary deposition module: for performing gate oxidation to the inner surface of the first trench region and the second trench region, depositing semi-insulating material inside and etching back, and depositing a second HM layer on the polysilicon;

[0068] CMP module: for implementing CMP to form ion implantation regions;

[0069] Self-alignment module: for self-aligned etching of the contact hole and front metal.

[0070] The application provides a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to realize the steps of the IGBT device method.

[0071] Embodiment 2

[0072] The first HM layer thickness is 0.6 um, the first HM layer interval is 0.7 um, the etching angle of the second trench region is 75°, the size of the top opening of the trench can be 0.95 um, and the test saturation pressure drop is 1.75 V.

[0073] Example 3

[0074] The first HM layer thickness is 0.8 um, the first HM layer interval is 0.7 um, the etching angle of the second trench region is 80°, the size of the top opening of the trench can be 0.85 um, and the test saturation pressure drop is 1.83 V.

[0075] Example 4

[0076] The first HM layer thickness is 0.6 um, the first HM layer interval is 0.8 um, the etching angle of the second trench region is 80°, the size of the top opening of the trench can be 0.9 um, and the test saturation pressure drop is 1.79 V.

[0077] Comparative Example 1

[0078] The first HM layer interval is 0.4 um, the size of the top opening of the trench can be 0.6 um, and the test saturation pressure drop is 1.95 V.

[0079] Comparative Example 2

[0080] The etching angle of the second trench region is 89°, the size of the top opening of the trench can be 0.7 um, and the test saturation pressure drop is 1.92 V.

[0081] Comparative Example 3

[0082] The first HM layer thickness is 0.3 um, the size of the top opening of the trench can be 0.8 um, and the test saturation pressure drop is 1.9 V.

Claims

1. An IGBT device, characterized by, It comprises: a semiconductor substrate (1); a plurality of first trench regions (4) formed in the semiconductor substrate (1) at intervals, and a second trench region (5) formed above and communicated with the first trench region (4); the etching angle of the second trench region (5) is larger than that of the first trench region (4) and both are acute angles; a gate oxide layer (6) formed on the inner surface of the first and second trench regions; a semi-insulating material layer (7) grown in the first and second trench regions for connecting the gate potential; an ion implantation layer formed between every interval trench region, from bottom to top, it is CS layer (9), Pwell layer (10) and NSD layer (11) in turn; a contact hole (12) penetrating from top to bottom and connecting the NSD layer (11) and the Pwell layer (10); the contact hole (12) is filled with a metal contact layer (13).

2. The IGBT device of claim 1, wherein, The etching angle of the first trench region (4) is 80-90°, and the trench depth is 3-5um; the etching angle of the second trench region (5) is 70-80°, and the trench depth is 1-3um.

3. The IGBT device of claim 1, wherein, The etching angle of the contact hole (12) is 70-90°, and the depth is 0.3-0.6um.

4. The IGBT device of claim 1, wherein, The top of the semi-insulating material layer (7) grown in the second trench region (5) is a shape of two sides high and middle low with the middle inwardly concave.

5. A method of manufacturing the IGBT device of claim 1, characterized by, It comprises the following steps: (A) depositing a plurality of first HM layers (2) on the semiconductor substrate (1) at intervals; (B) forming side walls (3) on both sides of the first HM layer (2); (C) etching downward the semiconductor substrate (1) region between adjacent first HM layers (2) to form a first trench region (4); (D) removing the side walls (3) on both sides of the first HM layer (2), and etching a second trench region (5) above the first trench region (4); (E) forming a gate oxide layer (6) on the inner surface of the first and second trench regions (4) and (5), then depositing a semi-insulating material layer (7) into the first and second trench regions (4) and (5), and performing back etching; (F) depositing a second HM layer (8) on the structure obtained in step (E); (G) performing CMP to the surface of the semiconductor substrate (1) to form an ion implantation region; (H) performing ion implantation to form CS layer (9), Pwell layer (10) and NSD layer (11) in turn from bottom to top; (I) using the gate oxide layer (6) between every interval trench region as a mask layer to etch a contact hole (12); (J) completing the front metalization.

6. The method of manufacturing an IGBT device according to claim 5, wherein The etching angle of the first trench region (4) is 80-90°, and the trench depth is 3-5um; the etching angle of the second trench region (5) is 70-80°, and the trench depth is 1-3um.

7. The method of claim 5, wherein the step of forming the IGBT device further comprises the step of: The thickness of the first HM layer (2) is 0.5-1um; the lateral distance between adjacent first HM layers (2) is 0.6-0.8um; the thickness of the second HM layer (8) is 0.5-1um. ​ 8. The method of claim 5, wherein the GBT device is a GBT transistor. The injection dose of the CS layer (9), the Pwell layer (10) and the NSD layer (11) in step (H) is respectively: 1e12-3e13 cm -3 , 1e13-3e13 cm -3 , 1e15-3e15 cm -3 The annealing conditions are respectively: 1150-1250℃, 100-300min; 1100-1150℃, 100-300min; 850-950℃, 30-60min.

9. A system for fabricating an IGBT device as claimed in claim 1, characterized in that, It comprises the following modules: substrate module for providing a semiconductor substrate (1); first deposition module for depositing a first HM layer (2) and forming a side wall (3) on the side of the first HM layer (2); trench module for forming a second trench area (5) and a first trench area (4) in sequence from the top of the semiconductor substrate (1) downwards; second deposition module for forming a gate oxide layer (6) on the inner surface of the first trench area (4) and the second trench area (5), depositing a semi-insulating material layer (7) into the two trench areas, etching back and depositing a second HM layer (8); CMP module for performing CMP and forming an ion implantation area; self-alignment module for self-alignment etching a contact hole (12) and front side metallization.

10. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program, which is executed by a processor, implements the steps of the method according to any one of claims 5 to 8.

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