Semi-insulating silicon carbide epitaxial wafer and preparation method thereof, and semiconductor device and preparation method thereof

Abstract

The invention discloses a semi-insulating silicon carbide epitaxial wafer and a preparation method thereof, a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle. At least one semi-insulating silicon carbide epitaxial layer located on one side of the substrate; and the first epitaxial layer is positioned on one side, far away from the substrate, of the at least one semi-insulating silicon carbide epitaxial layer. The semi-insulating silicon carbide epitaxial material can be effectively prepared, the quality of the first epitaxial layer is improved, the defects of the first epitaxial layer are reduced, and therefore the preparation requirements of different devices are met.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a semi-insulating silicon carbide epitaxial wafer and a preparation method thereof, a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle. BACKGROUND

[0002] At present, silicon carbide epitaxial growth is mainly aimed at epitaxial growth and preparation of N-type silicon carbide or P-type silicon carbide. For semi-insulating silicon carbide materials, semi-insulating silicon carbide crystals are mainly prepared, and therefore how to prepare semi-insulating silicon carbide epitaxial materials is a technical problem that needs to be solved in the industry. SUMMARY

[0003] The present application provides a semi-insulating silicon carbide epitaxial wafer and a preparation method thereof, a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle, to solve the problem that semi-insulating silicon carbide epitaxial materials cannot be prepared at present.

[0004] In a first aspect, the present application provides a semi-insulating silicon carbide epitaxial wafer, which comprises:

[0005] a substrate;

[0006] at least one semi-insulating silicon carbide epitaxial layer located on one side of the substrate;

[0007] a first epitaxial layer located on a side of the at least one semi-insulating silicon carbide epitaxial layer away from the substrate.

[0008] Optionally, the semi-insulating silicon carbide epitaxial wafer comprises at least two semi-insulating silicon carbide epitaxial layers; and the semi-insulating silicon carbide epitaxial wafer further comprises a second epitaxial layer.

[0009] The second epitaxial layer is located between adjacent semi-insulating silicon carbide epitaxial layers.

[0010] Optionally, the substrate comprises a silicon substrate, and the semi-insulating silicon carbide epitaxial wafer comprises a semi-insulating 3C-SiC epitaxial layer; or the substrate comprises a 6H-SiC substrate, and the semi-insulating silicon carbide epitaxial layer comprises a semi-insulating 4H-SiC epitaxial layer; or the substrate comprises a 3C-SiC substrate, and the semi-insulating silicon carbide epitaxial layer comprises a semi-insulating 4H-SiC epitaxial layer; or the substrate comprises a 4H-SiC substrate, and the semi-insulating silicon carbide epitaxial layer comprises a semi-insulating 3C-SiC epitaxial layer.

[0011] In a second aspect, the present application provides a preparation method of a semi-insulating silicon carbide epitaxial wafer, which comprises:

[0012] providing a substrate;

[0013] forming at least one semi-insulating silicon carbide epitaxial layer on one side of the substrate;

[0014] forming a first epitaxial layer on a side of the at least one semi-insulating silicon carbide epitaxial layer away from the substrate.

[0015] Optionally, forming the at least one semi-insulating silicon carbide epitaxial layer on a side of the substrate comprises:

[0016] forming the at least one semi-insulating silicon carbide epitaxial layer on a side of the substrate using any one of chemical vapor deposition, physical vapor deposition, pulsed laser deposition, atomic layer deposition or molecular beam epitaxy, using a compound containing vanadium or a compound containing iron as a dopant source.

[0017] Optionally, forming the at least one semi-insulating silicon carbide epitaxial layer on a side of the substrate comprises:

[0018] forming a semi-insulating silicon carbide epitaxial layer on a side of the substrate;

[0019] forming a second epitaxial layer on a side of the semi-insulating silicon carbide epitaxial layer away from the substrate at least once; and forming a semi-insulating silicon carbide epitaxial layer on a side of the second epitaxial layer away from the substrate.

[0020] Optionally, forming the at least one semi-insulating silicon carbide epitaxial layer on a side of the substrate comprises:

[0021] forming at least one semi-insulating 3C-SiC epitaxial layer on a side of a silicon substrate; or forming at least one semi-insulating 4H-SiC epitaxial layer on a side of a 6H-SiC substrate; or forming at least one semi-insulating 4H-SiC epitaxial layer on a side of a 3C-SiC substrate; or forming at least one semi-insulating 3C-SiC epitaxial layer on a side of a 4H-SiC substrate.

[0022] In a third aspect, the present application provides a semiconductor device, the semiconductor device comprising:

[0023] a semiconductor body comprising a first surface and a second surface arranged opposite to each other, the semiconductor body further comprising a substrate, a first semi-insulating silicon carbide epitaxial layer, a first epitaxial layer, a well region and a first region, the substrate being located at the second surface, the first semi-insulating silicon carbide epitaxial layer being located on a side of the substrate away from the second surface, the first epitaxial layer being located on a side of the first semi-insulating silicon carbide epitaxial layer away from the second surface, the well region being located on a side of the first epitaxial layer away from the second surface, the first region being located on a side of the well region away from the second surface and at the first surface, the semiconductor body further comprising a first insulating layer, the first insulating layer being located at the first surface or extending from the first surface into the semiconductor body;

[0024] a gate located on a side of the first insulating layer away from the semiconductor body;

[0025] a second insulating layer located at a side of the gate away from the semiconductor body; the second insulating layer covers a vertical projection of the gate on the first surface in a vertical direction;

[0026] a source located at the first surface;

[0027] a drain located at the second surface.

[0028] In a fourth aspect, the present application provides a method for manufacturing a semiconductor device, the method comprising:

[0029] providing a semiconductor body; the semiconductor body comprises oppositely arranged first and second surfaces, and further comprises a substrate, a first semi-insulating silicon carbide epitaxial layer, a first epitaxial layer, a well region and a first region; the substrate is located at the second surface; the first semi-insulating silicon carbide epitaxial layer is located at a side of the substrate away from the second surface; the first epitaxial layer is located at a side of the first semi-insulating silicon carbide epitaxial layer away from the second surface; the well region is located at a side of the first epitaxial layer away from the second surface; and the first region is located at a side of the well region away from the second surface and at the first surface; the semiconductor body further comprises a first insulating layer, which is located at the first surface or extends from the first surface into the semiconductor body;

[0030] forming a gate at a side of the first insulating layer away from the semiconductor body;

[0031] forming a second insulating layer at a side of the gate away from the semiconductor body; the second insulating layer covers a vertical projection of the gate on the first surface in a vertical direction;

[0032] forming a source at the first surface;

[0033] forming a drain at the second surface.

[0034] In a fifth aspect, the present application provides a semiconductor device, which comprises:

[0035] a semiconductor body; the semiconductor body comprises oppositely arranged first and second surfaces, and further comprises a substrate, a first semi-insulating silicon carbide epitaxial layer, a first epitaxial layer and a first region; the substrate is located at the second surface; the first semi-insulating silicon carbide epitaxial layer is located at a side of the substrate away from the second surface; the first epitaxial layer is located at a side of the first semi-insulating silicon carbide epitaxial layer away from the second surface; and the first region is located at a side of the first epitaxial layer away from the second surface and at the first surface;

[0036] an anode located at the first surface;

[0037] a cathode located at the second surface.

[0038] Optionally, the semiconductor body further comprises a second semi-insulating silicon carbide epitaxial layer and a second epitaxial layer.

[0039] The second semi-insulating silicon carbide epitaxial layer is located on the substrate and away from the second surface, and the second epitaxial layer is located on the second semi-insulating silicon carbide epitaxial layer and away from the second surface.

[0040] In a sixth aspect, the present application provides a method for manufacturing a semiconductor device, the method comprising:

[0041] providing a semiconductor body, the semiconductor body comprising a first surface and a second surface arranged opposite to each other, the semiconductor body further comprising a substrate, a first semi-insulating silicon carbide epitaxial layer, a first epitaxial layer and a first region, the substrate being located on the second surface, the first semi-insulating silicon carbide epitaxial layer being located on the substrate and away from the second surface, the first epitaxial layer being located on the first semi-insulating silicon carbide epitaxial layer and away from the second surface, the first region being located on the first epitaxial layer and away from the second surface and on the first surface;

[0042] forming an anode on the first surface;

[0043] forming a cathode on the second surface.

[0044] Optionally, the semiconductor body is provided, comprising:

[0045] a compound containing vanadium or a compound containing iron is used as a doping source to form the first semi-insulating silicon carbide epitaxial layer on the substrate and away from the second surface by any one of chemical vapor deposition, physical vapor deposition, pulsed laser deposition, atomic layer deposition or molecular beam epitaxy.

[0046] In a seventh aspect, the present application provides a power module, wherein the power module comprises a substrate and at least one semiconductor device as provided in the third aspect or the fifth aspect, the substrate being configured to support the semiconductor device.

[0047] In an eighth aspect, the present application provides a power conversion circuit, the power conversion circuit being configured to perform one or more of current conversion, voltage conversion and power factor correction.

[0048] The power conversion circuit comprises a circuit board and at least one semiconductor device as provided in the third aspect or the fifth aspect, the semiconductor device being electrically connected to the circuit board.

[0049] In a ninth aspect, the present application provides a vehicle, wherein the vehicle comprises a load and a power conversion circuit as provided in the eighth aspect, the power conversion circuit being configured to convert alternating current into direct current, convert alternating current into alternating current, convert direct current into direct current or convert direct current into alternating current before inputting to the load.

[0050] The technical scheme of the embodiment of the present application, the semi-insulating silicon carbide epitaxial wafer comprises a substrate, at least one semi-insulating silicon carbide epitaxial layer arranged on one side of the substrate, and a first epitaxial layer arranged on the side of the at least one semi-insulating silicon carbide epitaxial layer away from the substrate. By arranging the at least one semi-insulating silicon carbide epitaxial layer on one side of the substrate, the quality of the first epitaxial layer can be improved, and the defects of the first epitaxial layer can be reduced, so as to meet the preparation requirements of different devices. The technical scheme of the embodiment of the present application, by arranging the at least one semi-insulating silicon carbide epitaxial layer on one side of the substrate, any one of chemical vapor deposition (CVD), physical vapor deposition (PVD), pulsed laser deposition (PLD), atomic layer deposition (ALD) or molecular beam epitaxy (MBE) process can be used, a compound containing vanadium element or a compound containing iron element is used as a doping source, in-situ doping is performed during epitaxial growth, so that the at least one semi-insulating silicon carbide epitaxial layer is formed by epitaxy, without using secondary processes such as annealing, the semi-insulating silicon carbide epitaxial material can be effectively formed, and the preparation process of the silicon carbide epitaxial material is effectively simplified.

[0051] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present application, nor is it used to limit the scope of the present application. Other features of the present application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0052] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0053] Figure 1 is a structural schematic diagram of a semi-insulating silicon carbide epitaxial wafer provided by an embodiment of the present application;

[0054] Figure 2 is a structural schematic diagram of another semi-insulating silicon carbide epitaxial wafer provided by an embodiment of the present application;

[0055] Figure 3 is a flowchart of a preparation method of a semi-insulating silicon carbide epitaxial wafer provided by an embodiment of the present application;

[0056] Figures 4-5 is a structural schematic diagram corresponding to part of steps in a preparation method of a semi-insulating silicon carbide epitaxial wafer provided by an embodiment of the present application;

[0057] Figure 6 is a flowchart of another preparation method of a semi-insulating silicon carbide epitaxial wafer provided by an embodiment of the present application;

[0058] Figure 7 is a flow chart of another method for manufacturing a semi-insulating silicon carbide epitaxial wafer provided by an embodiment of the present application;

[0059] Figures 8-9 is a structural schematic diagram corresponding to part of steps in the method for manufacturing a semi-insulating silicon carbide epitaxial wafer provided by an embodiment of the present application;

[0060] Figure 10 is a flow chart of another method for manufacturing a semi-insulating silicon carbide epitaxial wafer provided by an embodiment of the present application;

[0061] Figure 11 is a structural schematic diagram of a semiconductor device provided by an embodiment of the present application;

[0062] Figure 12 is a flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present application;

[0063] Figures 13-16 is a structural schematic diagram corresponding to part of steps in the method for manufacturing a semiconductor device provided by an embodiment of the present application;

[0064] Figure 17 is a structural schematic diagram of another semiconductor device provided by an embodiment of the present application;

[0065] Figure 18 is a structural schematic diagram of another semiconductor device provided by an embodiment of the present application;

[0066] Figure 19 is a structural schematic diagram of another semiconductor device provided by an embodiment of the present application;

[0067] Figure 20 is another method for manufacturing a semiconductor device provided by an embodiment of the present application;

[0068] Figures 21-22 is a structural schematic diagram corresponding to part of steps in the method for manufacturing a semiconductor device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0069] In order to enable persons skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by persons skilled in the art without creative labor should fall within the protection scope of the present application.

[0070] It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting, unless the context clearly indicates otherwise. It will be further understood that the use of relational terms such as first and second, and the like, are used solely to distinguish one from another entity without necessarily implying a relationship or order between these entities. Moreover, the terms "comprises", "comprising", and "including", as well as variations thereof, do not have a limiting meaning and include both the process steps described in the claims and the process steps inherent to the process steps described in the claims. In other words, use of the term "comprises" or "comprising" does not mean that the method includes each and every recited step, but rather that the method includes at least the recited steps.

[0071] The method for preparing semi-insulating silicon carbide crystal includes: one is to compensate the shallow level impurities of nitrogen, boron and aluminum existing in the crystal by introducing doped elements, a small amount of solid vanadium is added into silicon carbide powder in the process of physical vapor transport (PVT) growth, and the silicon carbide powder and the vanadium are mixed uniformly through grinding and stirring, when the temperature reaches 2100 DEG C or above, the silicon carbide powder and the metal vanadium are sublimated and deposited and grown on the silicon carbide seed crystal, so that the vanadium is successfully introduced into the silicon carbide crystal. The other is a "high-purity semi-insulating silicon carbide" with unintentional element doping, which forms high-concentration deep level intrinsic point defects of Vc, Vsi, VcVsi and VcCsi types through crystal growth and annealing process, and is used to compensate the shallow level impurities of nitrogen (N), boron (B) and aluminum (Al).

[0072] The first preparation method cannot prepare semi-insulating silicon carbide epitaxial material, and the second method can be used for the preparation of semi-insulating silicon carbide epitaxial material, but the silicon carbide epitaxial growth in the second method has a strong background doping effect, the unintentionally doped silicon carbide epitaxial material shows N-type property, and the annealing process after epitaxial growth cannot necessarily make the silicon carbide epitaxial material into semi-insulating silicon carbide epitaxial material, and the annealing process is a secondary process, which increases the complexity of the preparation of the silicon carbide epitaxial material.

[0073] To solve the above problems, the technical scheme of the embodiment of the present application is as follows:

[0074] Figure 1 It is a structure diagram of a semi-insulating silicon carbide epitaxial wafer provided by the embodiment of the present application, as shown in Figure 1 The semi-insulating silicon carbide epitaxial wafer includes: a substrate 11, at least one semi-insulating silicon carbide epitaxial layer 12 located on one side of the substrate 11, and a first epitaxial layer 13 located on the side of the at least one semi-insulating silicon carbide epitaxial layer 12 away from the substrate 11.

[0075] Specifically, the semi-insulating silicon carbide epitaxial wafer can include a substrate 11, a semi-insulating silicon carbide epitaxial layer 12 and a first epitaxial layer 13, and the semi-insulating silicon carbide epitaxial wafer includes at least one semi-insulating silicon carbide epitaxial layer 12, Figure 1 The semi-insulating silicon carbide epitaxial wafer is exemplarily shown to include two semi-insulating silicon carbide epitaxial layers 12. In some embodiments of the present application, the semi-insulating silicon carbide epitaxial wafer can include one semi-insulating silicon carbide epitaxial layer 12, or more than two semi-insulating silicon carbide epitaxial layers 12. The semi-insulating silicon carbide epitaxial layer 12 is arranged on the side of the first epitaxial layer 13 close to the substrate 11, which can effectively improve the quality of the first epitaxial layer 13 and reduce the defects of the first epitaxial layer 13.

[0076] The semi-insulating silicon carbide epitaxial layer 12 can be prepared by using a compound containing vanadium (V) element or a compound containing iron (Fe) element as a doping source. The compound containing V element includes, for example, VH, V2H, V3H, VCl4, VCl3, C 10 H 10 V, etc., and the compound containing Fe element includes, for example, FeCl3, FeCl2, C 14 H 18 Fe, C 16 H 22 Fe, C 12 H 14 Fe, Fe(C5H5)2, etc. The doping concentration of the semi-insulating silicon carbide epitaxial layer 12 in different layers of the semi-insulating silicon carbide epitaxial wafer can be the same or different.

[0077] The substrate 11 can include a silicon substrate or a silicon carbide substrate, and the first epitaxial layer 12 can include a silicon epitaxial layer or a silicon carbide epitaxial layer. The conductivity type of the substrate 11 and the first epitaxial layer 12 can be the same or different, and can be doped according to the specific device preparation requirements. Exemplarily, the substrate 11 can include an N-type substrate, and the first epitaxial layer 12 can include an N-type epitaxial layer.

[0078] In the preparation process of the semi-insulating silicon carbide epitaxial wafer, the substrate 11 is first placed in an epitaxial reaction chamber, in-situ etching treatment is performed on the substrate 11 placed in the epitaxial reaction chamber, then in the epitaxial reaction chamber, any one of chemical vapor deposition (CVD), physical vapor deposition (PVD), pulsed laser deposition (PLD), atomic layer deposition (ALD) or molecular beam epitaxy (MBE) process is used, a compound containing vanadium elements or a compound containing iron elements is used as a doping source, in-situ doping is performed during epitaxial growth, thereby epitaxial growth of the semi-insulating silicon carbide epitaxial layer 12 on one side of the substrate 11, and then the semi-insulating silicon carbide epitaxial layer 12 is used as a doping source, epitaxial growth of the semi-insulating silicon carbide epitaxial layer 12 is performed on the side of the semi-insulating silicon carbide epitaxial layer 12 away from the substrate 11 by using any one of chemical vapor deposition (CVD), physical vapor deposition (PVD), pulsed laser deposition (PLD), atomic layer deposition (ALD) or molecular beam epitaxy (MBE) process. In the epitaxial growth of the semi-insulating silicon carbide epitaxial layer 12, the mass flow controller (MFC) and other methods can be used to control the concentration of the doping element, so as to achieve accurate control of the doping element, more convenient preparation of the semi-insulating silicon carbide epitaxial layer 12, and epitaxial growth of the semi-insulating silicon carbide epitaxial layer 12 with different doping concentrations in multiple layers to meet different device design requirements. For example, the chemical vapor deposition (CVD) process can include a high-temperature chemical vapor deposition process, and the semi-insulating silicon carbide epitaxial layer 12 is epitaxially grown by the high-temperature chemical vapor deposition process.

[0079] The technical scheme of the embodiment of the present application, the semi-insulating silicon carbide epitaxial wafer includes a substrate 11, at least one semi-insulating silicon carbide epitaxial layer 12 located on one side of the substrate 11, and a first epitaxial layer 13 located on the side of the at least one semi-insulating silicon carbide epitaxial layer 12 away from the substrate 11. By arranging at least one semi-insulating silicon carbide epitaxial layer 12 on one side of the substrate 11, the semi-insulating silicon carbide epitaxial material can be effectively prepared, the quality of the first epitaxial layer 13 can be improved, and the defects of the first epitaxial layer 13 can be reduced, thereby meeting the preparation requirements of different devices. In the embodiment of the present application, at least one semi-insulating silicon carbide epitaxial layer 12 is arranged on one side of the substrate 11, any one of chemical vapor deposition (CVD), physical vapor deposition (PVD), pulsed laser deposition (PLD), atomic layer deposition (ALD) or molecular beam epitaxy (MBE) process is used, a compound containing vanadium elements or a compound containing iron elements is used as a doping source, in-situ doping is performed during epitaxial growth, thereby epitaxial formation of the at least one semi-insulating silicon carbide epitaxial layer 12, without the need for secondary processes such as annealing, the semi-insulating silicon carbide epitaxial material can be effectively formed, and the preparation process of the silicon carbide epitaxial material is effectively simplified.

[0080] Optionally, based on each of the above embodiments, Figure 2is another structural schematic diagram of a semi-insulating silicon carbide epitaxial wafer provided by an embodiment of the present application, as shown in the figure, the semi-insulating silicon carbide epitaxial wafer comprises at least two semi-insulating silicon carbide epitaxial layers 12. The semi-insulating silicon carbide epitaxial wafer further comprises a second epitaxial layer 18. The second epitaxial layer 18 is located between adjacent semi-insulating silicon carbide epitaxial layers 12. Figure 2

[0081] Specifically, the semi-insulating silicon carbide epitaxial wafer can comprise at least two semi-insulating silicon carbide epitaxial layers 12, at this time, the semi-insulating silicon carbide epitaxial wafer can further comprise a second epitaxial layer 18, the second epitaxial layer 18 is arranged between adjacent semi-insulating silicon carbide epitaxial layers 12, and the number of the semi-insulating silicon carbide epitaxial layers 12 and the second epitaxial layer 18 can be set according to actual device requirements. The second epitaxial layer 18 and the semi-insulating silicon carbide epitaxial layer 12 can both serve as buffer layers, which can effectively improve the quality of the first epitaxial layer 13 and reduce defects of the first epitaxial layer 13.

[0082] The second epitaxial layer 18 can comprise a silicon epitaxial layer or a silicon carbide epitaxial layer, and the second epitaxial layer 18 can have the same or different conductivity type as the first epitaxial layer 13. For example, the substrate 11 can comprise an N-type substrate, the first epitaxial layer 12 can comprise an N-type epitaxial layer, and the second epitaxial layer 18 can comprise an N-type epitaxial layer.

[0083] In the preparation process of the semi-insulating silicon carbide epitaxial wafer provided by the embodiment of the present application, any one of chemical vapor deposition (CVD), physical vapor deposition (PVD), pulsed laser deposition (PLD), atomic layer deposition (ALD), or molecular beam epitaxy (MBE) process can be used to epitaxially grow the semi-insulating silicon carbide epitaxial layer 12 on one side of the substrate 11 by using a compound containing vanadium elements or a compound containing iron elements as a doping source, then epitaxially grow the second epitaxial layer 18 on the semi-insulating silicon carbide epitaxial layer 12, and then epitaxially grow the semi-insulating silicon carbide epitaxial layer 12 on the side of the second epitaxial layer 18 away from the substrate 11 by using any one of chemical vapor deposition (CVD), physical vapor deposition (PVD), pulsed laser deposition (PLD), atomic layer deposition (ALD), or molecular beam epitaxy (MBE) process, using a compound containing vanadium elements or a compound containing iron elements as a doping source. The embodiment of the present application can effectively prepare and form a semi-insulating silicon carbide epitaxial material, thereby meeting the preparation requirements of different devices. Moreover, no secondary process such as annealing is required, which can effectively form a semi-insulating silicon carbide epitaxial material and effectively simplify the preparation process of the silicon carbide epitaxial material.

[0084] Optionally, on the basis of each of the above embodiments, reference is continued to Figure 1 and Figure 2 ​, the substrate 11 comprises a silicon substrate, and the semi-insulating silicon carbide epitaxial layer 12 comprises a semi-insulating 3C-SiC epitaxial layer. Alternatively, the substrate 11 comprises a 6H-SiC substrate, and the semi-insulating silicon carbide epitaxial layer 12 comprises a semi-insulating 4H-SiC epitaxial layer. Alternatively, the substrate 11 comprises a 3C-SiC substrate, and the semi-insulating silicon carbide epitaxial layer 12 comprises a semi-insulating 4H-SiC epitaxial layer. Alternatively, the substrate 11 comprises a 4H-SiC substrate, and the semi-insulating silicon carbide epitaxial layer 12 comprises a semi-insulating 3C-SiC epitaxial layer.

[0085] Specifically, the substrate 11 and the semi-insulating silicon carbide epitaxial layer 12 can be made of different materials, i.e., the semi-insulating silicon carbide epitaxial layer 12 can be epitaxially formed on a hetero-substrate, and the substrate 11 is not a silicon carbide substrate. For example, the semi-insulating 3C-SiC epitaxial layer can be epitaxially formed on a silicon substrate by using a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a pulsed laser deposition (PLD) process, an atomic layer deposition (ALD) process, or a molecular beam epitaxy (MBE) process, and in-situ doping is performed during epitaxial growth by using a compound containing vanadium or a compound containing iron as a doping source.

[0086] The substrate 11 and the semi-insulating silicon carbide epitaxial layer 12 in the semi-insulating silicon carbide epitaxial wafer provided by the embodiment of the present application can both be silicon carbide materials, but the crystal types can be the same or different. For example, the semi-insulating 4H-SiC epitaxial layer can be epitaxially formed on a 6H-SiC substrate, or the semi-insulating 4H-SiC epitaxial layer can be epitaxially formed on a 3C-SiC substrate, or the semi-insulating 3C-SiC epitaxial layer can be epitaxially formed on a 4H-SiC substrate by using a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a pulsed laser deposition (PLD) process, an atomic layer deposition (ALD) process, or a molecular beam epitaxy (MBE) process, and in-situ doping is performed during epitaxial growth by using a compound containing vanadium or a compound containing iron as a doping source.

[0087] The technical solution of the embodiment of the present application can arbitrarily select the materials and crystal types of the substrate 11 and the semi-insulating silicon carbide epitaxial layer 12 according to the specific device preparation requirements, so as to meet the preparation requirements of different devices.

[0088] Optionally, on the basis of each of the above embodiments, continuing to refer to Figure 1 and Figure 2 , the semi-insulating silicon carbide epitaxial wafer can comprise at least two semi-insulating silicon carbide epitaxial layers 12, and the crystal types of the different semi-insulating silicon carbide epitaxial layers 12 can be the same or different.

[0089] Figure 3 is a flowchart of a method for preparing a semi-insulating silicon carbide epitaxial wafer provided by the embodiment of the present application, Figures 4-5is a structural diagram corresponding to part of steps in a preparation method of a semi-insulating silicon carbide epitaxial wafer provided by an embodiment of the present application, as shown in Figure 3 The preparation method comprises the following steps:

[0090] S100: providing a substrate.

[0091] Specifically, as shown in Figure 4 First, a substrate 11 is provided, which can include a silicon substrate or a silicon carbide substrate. The substrate 11 can be placed in an epitaxial reaction chamber first, and in-situ etching treatment is performed on the substrate 11 placed in the epitaxial reaction chamber.

[0092] S110: forming at least one semi-insulating silicon carbide epitaxial layer on one side of the substrate.

[0093] Specifically, as shown in Figure 5 In the epitaxial reaction chamber, any one of chemical vapor deposition (CVD), physical vapor deposition (PVD), pulsed laser deposition (PLD), atomic layer deposition (ALD) or molecular beam epitaxy (MBE) process is used to epitaxially grow a semi-insulating silicon carbide epitaxial layer 12 on one side of the substrate 11 by using a compound containing vanadium elements or a compound containing iron elements as a doping source during epitaxial growth. The epitaxial growth of the semi-insulating silicon carbide epitaxial layer 12 can continue by using any one of chemical vapor deposition (CVD), physical vapor deposition (PVD), pulsed laser deposition (PLD), atomic layer deposition (ALD) or molecular beam epitaxy (MBE) process on the side of the semi-insulating silicon carbide epitaxial layer 12 away from the substrate 11, using a compound containing vanadium elements or a compound containing iron elements as a doping source. The concentration of the doping element can be controlled by using a mass flow controller (MFC) or other methods during the epitaxial growth of the semi-insulating silicon carbide epitaxial layer 12 to achieve accurate control of the doping element, so as to more conveniently prepare the semi-insulating silicon carbide epitaxial layer 12, and the epitaxial growth of the semi-insulating silicon carbide epitaxial layer 12 with different doping concentrations can be performed to meet different device design requirements. For example, the chemical vapor deposition (CVD) process can include a high-temperature chemical vapor deposition process, and the semi-insulating silicon carbide epitaxial layer 12 is epitaxially grown by the high-temperature chemical vapor deposition process.

[0094] S120: forming a first epitaxial layer on the side of the at least one semi-insulating silicon carbide epitaxial layer away from the substrate.

[0095] Specifically, as shown in Figure 1 The first epitaxial layer 13 is formed on the side of the at least one semi-insulating silicon carbide epitaxial layer 12 away from the substrate 11. The first epitaxial layer 12 can include a silicon epitaxial layer or a silicon carbide epitaxial layer, and the conductivity type of the substrate 11 and the first epitaxial layer 12 can be the same or different.

[0096] The technical solution of the embodiment of the present invention can utilize any of the chemical vapor deposition (CVD), physical vapor deposition (PVD), pulsed laser deposition (PLD), atomic layer deposition (ALD), or molecular beam epitaxy (MBE) processes on one side of the substrate 11, using a vanadium-containing compound or an iron-containing compound as a doping source, and performing in-situ doping during the epitaxial growth process, thereby epitaxially forming at least one semi-insulating silicon carbide epitaxial layer 12. This can effectively prepare and form a semi-insulating silicon carbide epitaxial material, improve the quality of the first epitaxial layer 13, and reduce the defects of the first epitaxial layer 13, thereby meeting the preparation requirements of different devices. Semi-insulating silicon carbide epitaxial material can be effectively formed without the use of secondary processes such as annealing, and the preparation process of silicon carbide epitaxial material is effectively simplified.

[0097] Optionally, based on the above embodiments, Figure 6 is a flow chart of another method for preparing a semi-insulating silicon carbide epitaxial wafer provided by an embodiment of the present invention, such as Figure 6 As shown, the preparation method includes:

[0098] S200: providing a substrate.

[0099] S210: Using a vanadium-containing compound or an iron-containing compound as a doping source, and using any one of chemical vapor deposition, physical vapor deposition, pulsed laser deposition, atomic layer deposition or molecular beam epitaxy processes to form at least one semi-insulating silicon carbide epitaxial layer on one side of the substrate.

[0100] Specifically, such as Figure 5 As shown, in an epitaxial reaction chamber, any one of chemical vapor deposition (CVD), physical vapor deposition (PVD), pulsed laser deposition (PLD), atomic layer deposition (ALD) or molecular beam epitaxy (MBE) processes is used, and a vanadium-containing compound or an iron-containing compound is used as a doping source to perform in-situ doping during the epitaxial growth process, thereby epitaxially growing a semi-insulating silicon carbide epitaxial layer 12 on one side of the substrate 11. Any one of chemical vapor deposition (CVD), physical vapor deposition (PVD), pulsed laser deposition (PLD), atomic layer deposition (ALD) or molecular beam epitaxy (MBE) processes can be used on the side of the semi-insulating silicon carbide epitaxial layer 12 away from the substrate 11, and a vanadium-containing compound or an iron-containing compound is used as a doping source to epitaxially grow the semi-insulating silicon carbide epitaxial layer 12. When epitaxially growing the semi-insulating silicon carbide epitaxial layer 12, the concentration of the doping elements can be controlled by using methods such as a mass flow controller (MFC) to achieve precise control of the doping elements, so as to more conveniently prepare the semi-insulating silicon carbide epitaxial layer 12, and epitaxial growth of multiple layers of semi-insulating silicon carbide epitaxial layers 12 with different doping concentrations can be performed to meet different device design requirements.

[0101] S220: forming a first epitaxial layer on a side of at least one semi-insulating silicon carbide epitaxial layer away from the substrate.

[0102] Optionally, Figure 7 This is a flow chart of another method for preparing a semi-insulating silicon carbide epitaxial wafer provided by an embodiment of the present invention. Figures 8-9 Schematic diagram of the structure corresponding to some steps in another method for preparing a semi-insulating silicon carbide epitaxial wafer provided by an embodiment of the present invention, such as Figure 7 As shown, the preparation method includes:

[0103] S300: providing a substrate.

[0104] S310: forming a semi-insulating silicon carbide epitaxial layer on one side of the substrate.

[0105] Specifically, such as Figure 8 As shown, in an epitaxial reaction chamber, any one of chemical vapor deposition (CVD), physical vapor deposition (PVD), pulsed laser deposition (PLD), atomic layer deposition (ALD) or molecular beam epitaxy (MBE) processes is used, and a vanadium-containing compound or an iron-containing compound is used as a doping source. In-situ doping is performed during the epitaxial growth process, thereby epitaxially growing a semi-insulating silicon carbide epitaxial layer 12 on one side of the substrate 11.

[0106] S320: forming a second epitaxial layer at least once on a side of the semi-insulating silicon carbide epitaxial layer away from the substrate; and forming another semi-insulating silicon carbide epitaxial layer on a side of the second epitaxial layer away from the substrate.

[0107] Specifically, such as Figure 9 As shown, the semi-insulating silicon carbide epitaxial wafer may include at least two semi-insulating silicon carbide epitaxial layers 12. In this case, the semi-insulating silicon carbide epitaxial wafer may also include a second epitaxial layer 18, which is disposed between adjacent semi-insulating silicon carbide epitaxial layers 12. The number of semi-insulating silicon carbide epitaxial layers 12 and second epitaxial layers 18 can be set according to actual device requirements. Both the second epitaxial layer 18 and the semi-insulating silicon carbide epitaxial layer 12 can serve as buffer layers, effectively improving the quality of the first epitaxial layer 13 and reducing defects in the first epitaxial layer 13.

[0108] The second epitaxial layer 18 may include a silicon epitaxial layer or a silicon carbide epitaxial layer. The conductivity type of the second epitaxial layer 18 may be the same as or different from the conductivity type of the first epitaxial layer 13. For example, the substrate 11 may include an N-type substrate, the first epitaxial layer 12 may include an N-type epitaxial layer, and the second epitaxial layer 18 may include an N-type epitaxial layer.

[0109] On the side of the second epitaxial layer 18 away from the substrate 11, a semi-insulating silicon carbide epitaxial layer 12 is epitaxially grown using any of the chemical vapor deposition (CVD), physical vapor deposition (PVD), pulsed laser deposition (PLD), atomic layer deposition (ALD) or molecular beam epitaxy (MBE) processes, using a vanadium-containing compound or an iron-containing compound as a doping source. The embodiment of the present invention can effectively prepare and form a semi-insulating silicon carbide epitaxial material, thereby meeting the preparation requirements of different devices. And without the need for secondary processes such as annealing, the semi-insulating silicon carbide epitaxial material can be effectively formed, and the preparation process of the silicon carbide epitaxial material is effectively simplified.

[0110] S330: forming a first epitaxial layer on a side of at least one semi-insulating silicon carbide epitaxial layer away from the substrate.

[0111] Optionally, based on the above embodiments, Figure 10 This is a flow chart of another method for preparing a semi-insulating silicon carbide epitaxial wafer provided by an embodiment of the present invention, such as Figure 10 As shown, the preparation method includes:

[0112] S400: providing a substrate.

[0113] S410: forming at least one semi-insulating 3C-SiC epitaxial layer on one side of a silicon substrate; or forming at least one semi-insulating 4H-SiC epitaxial layer on one side of a 6H-SiC substrate; or forming at least one semi-insulating 4H-SiC epitaxial layer on one side of a 3C-SiC substrate; or forming at least one semi-insulating 3C-SiC epitaxial layer on one side of a 4H-SiC substrate.

[0114] Specifically, such as Figure 5 As shown, the materials of the substrate 11 and the semi-insulating silicon carbide epitaxial layer 12 provided in the embodiment of the present invention can be different, that is, the semi-insulating silicon carbide epitaxial layer 12 can be epitaxially formed on a foreign substrate, and the substrate 11 is not a silicon carbide substrate. For example, any one of chemical vapor deposition (CVD), physical vapor deposition (PVD), pulsed laser deposition (PLD), atomic layer deposition (ALD), or molecular beam epitaxy (MBE) processes can be used, using a vanadium-containing compound or an iron-containing compound as a doping source, to perform in-situ doping during the epitaxial growth process, thereby epitaxially forming a semi-insulating 3C-SiC epitaxial layer on a silicon substrate.

[0115] The substrate 11 and the semi-insulating silicon carbide epitaxial layer 12 in the semi-insulating silicon carbide epitaxial wafer provided by the embodiment of the present application can both be silicon carbide materials, but the crystal forms can be the same or different. For example, a chemical vapor deposition (CVD), a physical vapor deposition (PVD), a pulsed laser deposition (PLD), an atomic layer deposition (ALD), or a molecular beam epitaxy (MBE) process can be used to epitaxially form a semi-insulating 4H-SiC epitaxial layer on a 6H-SiC substrate, or a semi-insulating 4H-SiC epitaxial layer on a 3C-SiC substrate, or a semi-insulating 3C-SiC epitaxial layer on a 4H-SiC substrate, by using a compound containing vanadium or a compound containing iron as a doping source for in-situ doping during epitaxial growth.

[0116] S420: Forming a first epitaxial layer on a side of the at least one semi-insulating silicon carbide epitaxial layer away from the substrate.

[0117] Figure 11 is a structure diagram of a semiconductor device provided by the embodiment of the present application. As shown in Figure 11 the semiconductor device includes a semiconductor body 1, the semiconductor body 1 includes oppositely arranged first and second surfaces 101 and 102, and the semiconductor body 1 further includes a substrate 11, a first semi-insulating silicon carbide epitaxial layer, a first epitaxial layer, a well region, and a first region. The substrate is located at the second surface, the first semi-insulating silicon carbide epitaxial layer 121 is located on a side of the substrate 11 away from the second surface 102, the first epitaxial layer 13 is located on a side of the first semi-insulating silicon carbide epitaxial layer 121 away from the second surface 102, the well region 14 is located on a side of the first epitaxial layer 13 away from the second surface 102, and the first region 15 is located on a side of the well region 14 away from the second surface 102 and on the first surface 101. The semiconductor body 1 further includes a first insulating layer 17, which is located on the first surface 101 or extends from the first surface 101 into the semiconductor body 1. A gate 2 is located on a side of the first insulating layer 17 away from the semiconductor body 1. A second insulating layer 3 is located on a side of the gate 2 away from the semiconductor body 1, and a vertical projection of the second insulating layer 3 on the first surface 101 covers a vertical projection of the gate 2 on the first surface 101. A source 4 is located on the first surface 101. A drain 5 is located on the second surface 102.

[0118] It should be noted that the drawings of the embodiments of the present application are introduced by taking the planar MOSFET semiconductor device as an example, and in other embodiments, the single-trench MOSFET semiconductor device and the double-trench MOSFET semiconductor device are also applicable. In the single-trench MOSFET semiconductor device and the double-trench MOSFET semiconductor device, the first insulating layer 17 and the gate 2 extend from the first surface 101 into the semiconductor body 1. In the planar MOSFET semiconductor device, the first insulating layer 17 and the gate 2 are arranged on the first surface 101.

[0119] Specifically, the substrate 11, the first semi-insulating silicon carbide epitaxial layer 121 and the first epitaxial layer 13 in the MOSFET semiconductor device are in the structure of the semi-insulating silicon carbide epitaxial wafer, and the first semi-insulating silicon carbide epitaxial layer 121 is the semi-insulating silicon carbide epitaxial layer 12 provided in any of the above embodiments of the present application.

[0120] Optionally, as shown in FIG. 1, the semiconductor body 1 can further include a second region 16, and the doping concentration of the second region 16 is greater than the doping concentration of the well region 14, and the second region 16 can form a good ohmic contact with the source 4. Figure 11

[0121] It should be noted that the MOSFET semiconductor device can include an N-channel MOSFET semiconductor device or a P-channel MOSFET semiconductor device. For example, for the N-channel MOSFET semiconductor device, the semiconductor body 1 is an N-type semiconductor body, the well region 14 is a P-type well region, the first region 15 is an N+ doped region, and the second region 16 is a P+ doped region. For the P-channel MOSFET semiconductor device, the semiconductor body 1 is a P-type semiconductor body, the well region 14 is an N-type well region, the first region 15 is a P+ doped region, and the second region 16 is an N+ doped region.

[0122] For example, as shown in FIG. 1, the semiconductor body 1 can further include a substrate 11, a first semi-insulating silicon carbide epitaxial layer 121 and a first epitaxial layer 13. For the N-channel MOSFET semiconductor device, the substrate 11 includes an N+ substrate, and the first epitaxial layer 13 includes an N- epitaxial layer. For the P-channel MOSFET semiconductor device, the substrate 11 includes a P+ substrate, and the first epitaxial layer 13 includes a P- epitaxial layer. The first epitaxial layer 13 is a semiconductor layer formed on the basis of the first semi-insulating silicon carbide epitaxial layer 121 by a first epitaxial process, and the epitaxial process includes a chemical vapor phase epitaxy (CVE), a molecular beam epitaxy (MBE) and an atomic layer epitaxy (ALE) process. Figure 1

[0123] ​​The MOSFET semiconductor device provided by the embodiment of the present application, the first semi-insulating silicon carbide epitaxial layer 121 is arranged on the side of the first epitaxial layer 13 close to the substrate 11, which can effectively improve the quality of the first epitaxial layer 13 and reduce the defects of the first epitaxial layer 13. In the preparation process of the MOSFET semiconductor device, any one of the chemical vapor deposition (CVD), the physical vapor deposition (PVD), the pulsed laser deposition (PLD), the atomic layer deposition (ALD) or the molecular beam epitaxy (MBE) process can be used to epitaxially grow the first semi-insulating silicon carbide epitaxial layer 121 on the side of the substrate 11 by using a compound containing vanadium elements or a compound containing iron elements as a doping source for in-situ doping in the epitaxial growth process.

[0124] The technical scheme of the embodiment of the present application can effectively prepare the semi-insulating silicon carbide epitaxial material by arranging the first semi-insulating silicon carbide epitaxial layer 121 on the side of the substrate 11, improve the quality of the first epitaxial layer 13 and reduce the defects of the first epitaxial layer 13. The technical scheme of the embodiment of the present application can use any one of the chemical vapor deposition (CVD), the physical vapor deposition (PVD), the pulsed laser deposition (PLD), the atomic layer deposition (ALD) or the molecular beam epitaxy (MBE) process to epitaxially form the first semi-insulating silicon carbide epitaxial layer 121 by using a compound containing vanadium elements or a compound containing iron elements as a doping source for in-situ doping in the epitaxial growth process, without using the secondary process such as annealing, which can effectively form the semi-insulating silicon carbide epitaxial material and effectively simplify the preparation process of the silicon carbide epitaxial material.

[0125] Figure 12 is a flow chart of a preparation method of a semiconductor device provided by the embodiment of the present application, Figures 13-16 is a structure schematic diagram corresponding to part of steps in the preparation method of a semiconductor device provided by the embodiment of the present application, as shown in the figure, Figure 12 the preparation method comprises the following steps:

[0126] S500: providing a semiconductor body; the semiconductor body comprises oppositely arranged first and second surfaces, and further comprises a substrate, a first semi-insulating silicon carbide epitaxial layer, a first epitaxial layer, a well region and a first region, the substrate is located at the second surface, the first semi-insulating silicon carbide epitaxial layer is located at the side of the substrate away from the second surface, the first epitaxial layer is located at the side of the first semi-insulating silicon carbide epitaxial layer away from the second surface, the well region is located at the side of the first epitaxial layer away from the second surface, and the first region is located at the side of the well region away from the second surface and at the first surface; the semiconductor body further comprises a first insulating layer, which is located at the first surface or extends from the first surface into the semiconductor body.

[0127] Specifically, as shown inFigure 13 The preparation process of the planar MOSFET semiconductor device is introduced as an example, and the preparation process is also applicable to the single-trench MOSFET semiconductor device and the double-trench MOSFET semiconductor device in other embodiments. In the single-trench MOSFET semiconductor device and the double-trench MOSFET semiconductor device, the first insulating layer 17 and the gate 2 extend into the semiconductor body 1 from the first surface 101. In the planar MOSFET semiconductor device, the first insulating layer 17 and the gate 2 are arranged on the first surface 101.

[0128] The substrate 11 can be placed in an epitaxial reaction chamber, and in-situ etching is performed on the substrate 11 placed in the epitaxial reaction chamber. Then, in the epitaxial reaction chamber, in-situ doping is performed during epitaxial growth by using a chemical vapor deposition (CVD), a physical vapor deposition (PVD), a pulsed laser deposition (PLD), an atomic layer deposition (ALD), or a molecular beam epitaxy (MBE) process, and using a compound containing vanadium elements or a compound containing iron elements as a doping source, thereby epitaxially growing the first semi-insulating silicon carbide epitaxial layer 121 on one side of the substrate 11. The embodiment of the present application can effectively prepare the semi-insulating silicon carbide epitaxial material, improve the quality of the first epitaxial layer 13, and reduce the defects of the first epitaxial layer 13. Without using a secondary process such as annealing, the semi-insulating silicon carbide epitaxial material can be effectively prepared, and the preparation process of the silicon carbide epitaxial material is effectively simplified.

[0129] S510: Forming a gate on a side of the first insulating layer away from the semiconductor body.

[0130] Specifically, as shown in FIG. 1, the gate 2 is formed on a side of the first insulating layer 17 away from the semiconductor body 1. In the single-trench MOSFET semiconductor device and the double-trench MOSFET semiconductor device, the first insulating layer 17 and the gate 2 extend into the semiconductor body 1 from the first surface 101. In the planar MOSFET semiconductor device, the first insulating layer 17 and the gate 2 are arranged on the first surface 101. Figure 14 S520: Forming a second insulating layer on a side of the gate away from the semiconductor body; the vertical projection of the second insulating layer on the first surface covers the vertical projection of the gate on the first surface.

[0131] Specifically, as shown in FIG. 1, the second insulating layer 3 is formed on a side of the gate 2 away from the semiconductor body 1, and the second insulating layer 3 is used to insulate the gate 2 and the source.

[0132] Figure 15

[0133] S530: Forming a source on the first surface.

[0134] Specifically, as shown in FIG. 1, the source 4 is formed on the first surface 101. Figure 16 ​​As shown, a source 4 is formed on the first surface 101 .

[0135] S540: forming a drain on the second surface.

[0136] Specifically, such as Figure 11 As shown, a drain 5 is formed on the second surface 102 .

[0137] Figure 17 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention, such as Figure 17 As shown, the semiconductor device includes: a semiconductor body 1; the semiconductor body 1 includes a first surface 101 and a second surface 102 arranged opposite to each other, and the semiconductor body 1 also includes a substrate 11, a first semi-insulating silicon carbide epitaxial layer 121, a first epitaxial layer 13, and a first region 15. The substrate 11 is located on the second surface 102, the first semi-insulating silicon carbide epitaxial layer 121 is located on a side of the substrate 11 away from the second surface 102, the first epitaxial layer 13 is located on a side of the first semi-insulating silicon carbide epitaxial layer 121 away from the second surface 102, and the first region 15 is located on a side of the first epitaxial layer 13 away from the second surface 102 and is located on the first surface 101. An anode 6 is located on the first surface 101. A cathode 7 is located on the second surface 102.

[0138] Specifically, the substrate 11, the first semi-insulating silicon carbide epitaxial layer 121 and the first epitaxial layer 13 in the Schottky diode semiconductor device are semi-insulating silicon carbide epitaxial wafer structures, and the first semi-insulating silicon carbide epitaxial layer 121 is the semi-insulating silicon carbide epitaxial layer 12 provided in any of the above embodiments of the present invention.

[0139] It should be noted that the Schottky diode semiconductor device includes an N-channel Schottky diode semiconductor device or a P-channel Schottky diode semiconductor device. For example, for an N-channel Schottky diode semiconductor device, the semiconductor body 1 is an N-type semiconductor body, the first region 15 is a P+ doped region, the substrate 11 is an N+ substrate, and the first epitaxial layer 13 is an N- epitaxial layer.

[0140] In the Schottky diode semiconductor device provided by an embodiment of the present invention, the first semi-insulating silicon carbide epitaxial layer 121 is disposed on a side of the first epitaxial layer 13 close to the substrate 11, which can effectively improve the quality of the first epitaxial layer 13 and reduce defects in the first epitaxial layer 13. During the preparation process of the Schottky diode semiconductor device, any one of chemical vapor deposition (CVD), physical vapor deposition (PVD), pulsed laser deposition (PLD), atomic layer deposition (ALD), or molecular beam epitaxy (MBE) processes can be used in an epitaxial reaction chamber, using a vanadium-containing compound or an iron-containing compound as a doping source, and in-situ doping is performed during the epitaxial growth process, thereby epitaxially growing the first semi-insulating silicon carbide epitaxial layer 121 on one side of the substrate 11.

[0141] The technical scheme of the embodiment of the present application can effectively prepare and form the semi-insulating silicon carbide epitaxial material, improve the quality of the first epitaxial layer 13, and reduce the defects of the first epitaxial layer 13 by arranging the first semi-insulating silicon carbide epitaxial layer 121 on one side of the substrate 11. The technical scheme of the embodiment of the present application can use any one of the chemical vapor deposition (CVD), physical vapor deposition (PVD), pulsed laser deposition (PLD), atomic layer deposition (ALD), or molecular beam epitaxy (MBE) process, use a compound containing vanadium elements or a compound containing iron elements as a doping source, and perform in-situ doping during epitaxial growth, so as to epitaxially form the first semi-insulating silicon carbide epitaxial layer 121. Without using a secondary process such as annealing, the semi-insulating silicon carbide epitaxial material can be effectively formed, and the preparation process of the silicon carbide epitaxial material is effectively simplified.

[0142] Optionally, based on each of the above embodiments, Figure 18 is another structure schematic diagram of a semiconductor device provided by the embodiment of the present application, Figure 19 is another structure schematic diagram of a semiconductor device provided by the embodiment of the present application, as Figure 18 and Figure 19 As shown in FIG. 1, the semiconductor body 1 further includes a second semi-insulating silicon carbide epitaxial layer 122 and a second epitaxial layer 18. The second semi-insulating silicon carbide epitaxial layer 122 and the second epitaxial layer 18 are located between the substrate 11 and the first semi-insulating silicon carbide epitaxial layer 121. The second semi-insulating silicon carbide epitaxial layer 122 is located on the side of the substrate 11 away from the second surface 102, and the second epitaxial layer 18 is located on the side of the second semi-insulating silicon carbide epitaxial layer 122 away from the second surface 102.

[0143] Specifically, Figure 18 exemplarily shows another MOSFET semiconductor device structure, Figure 19 exemplarily shows another Schottky diode semiconductor device structure. The substrate 11, the second semi-insulating silicon carbide epitaxial layer 122, the second epitaxial layer 18, the first semi-insulating silicon carbide epitaxial layer 121, and the first epitaxial layer 13 constitute another semi-insulating silicon carbide epitaxial wafer structure. The second semi-insulating silicon carbide epitaxial layer 122 and the first semi-insulating silicon carbide epitaxial layer 121 are the semi-insulating silicon carbide epitaxial layer 12 provided by any one of the above embodiments of the present application.

[0144] The second epitaxial layer 18 can include a silicon epitaxial layer or a silicon carbide epitaxial layer, and the conductivity type of the second epitaxial layer 18 is the same as that of the first epitaxial layer 13 for the MOSFET semiconductor device and the Schottky diode semiconductor device. The second semi-insulating silicon carbide epitaxial layer 122, the second epitaxial layer 18 and the first semi-insulating silicon carbide epitaxial layer 121 can all serve as buffer layers, which can effectively improve the quality of the first epitaxial layer 13 and reduce defects of the first epitaxial layer 13.

[0145] In the preparation of the MOSFET semiconductor device and the Schottky diode semiconductor device provided by the embodiment of the present application, any one of chemical vapor deposition (CVD), physical vapor deposition (PVD), pulsed laser deposition (PLD), atomic layer deposition (ALD) or molecular beam epitaxy (MBE) process can be used to epitaxially grow the first semi-insulating silicon carbide epitaxial layer 121 on one side of the substrate 11 by using a compound containing vanadium or a compound containing iron as a doping source for in-situ doping during epitaxial growth, then epitaxially grow the second epitaxial layer 18 on the first semi-insulating silicon carbide epitaxial layer 121, and then epitaxially grow the second semi-insulating silicon carbide epitaxial layer 122 on the second epitaxial layer 18 away from the substrate 11 by using any one of chemical vapor deposition (CVD), physical vapor deposition (PVD), pulsed laser deposition (PLD), atomic layer deposition (ALD) or molecular beam epitaxy (MBE) process by using a compound containing vanadium or a compound containing iron as a doping source. The embodiment of the present application can effectively prepare the semi-insulating silicon carbide epitaxial material, thereby meeting the preparation requirements of different devices. Moreover, no secondary process such as annealing is needed, the semi-insulating silicon carbide epitaxial material can be effectively prepared, and the preparation process of the silicon carbide epitaxial material is effectively simplified.

[0146] Figure 20 is another preparation method of a semiconductor device provided by the embodiment of the present application, Figures 21-22 is a structure diagram corresponding to part of steps in the preparation method of another semiconductor device provided by the embodiment of the present application, as shown in Figure 20 The preparation method comprises the following steps:

[0147] S600: providing a semiconductor body; the semiconductor body comprises oppositely arranged first and second surfaces, and further comprises a substrate, a first semi-insulating silicon carbide epitaxial layer, a first epitaxial layer and a first region; the substrate is located at the second surface, the first semi-insulating silicon carbide epitaxial layer is located at a side of the substrate away from the second surface, the first epitaxial layer is located at a side of the first semi-insulating silicon carbide epitaxial layer away from the second surface, and the first region is located at a side of the first epitaxial layer away from the second surface and at the first surface.

[0148] Specifically, as shown in Figure 21As shown, the substrate 11 can be placed in an epitaxial reaction chamber first, and then in-situ etching treatment is performed on the substrate 11 placed in the epitaxial reaction chamber, and then in-situ doping is performed during epitaxial growth by using a chemical vapor deposition (CVD), a physical vapor deposition (PVD), a pulsed laser deposition (PLD), an atomic layer deposition (ALD) or a molecular beam epitaxy (MBE) process, using a compound containing vanadium elements or a compound containing iron elements as a doping source, so as to epitaxially grow the first semi-insulating silicon carbide epitaxial layer 121 on one side of the substrate 11. The embodiment of the present application can effectively prepare the semi-insulating silicon carbide epitaxial material, improve the quality of the first epitaxial layer 13, and reduce the defects of the first epitaxial layer 13. Without using secondary processes such as annealing, the semi-insulating silicon carbide epitaxial material can be effectively prepared, and the preparation process of the silicon carbide epitaxial material is effectively simplified.

[0149] S610: Form an anode on the first surface.

[0150] Specifically, as shown in the figure, Figure 22 an anode 6 is formed on the first surface 101.

[0151] S620: Form a cathode on the second surface.

[0152] Specifically, as shown in the figure, Figure 17 a cathode 7 is formed on the second surface 102.

[0153] The embodiment of the present application provides a power module, wherein the power module comprises a substrate and at least one semiconductor device provided by any one of the above-mentioned embodiments of the present application, and the substrate is used for carrying the at least one semiconductor device provided by any one of the above-mentioned embodiments of the present application.

[0154] The power module provided by any one of the above-mentioned embodiments of the present application comprises the semiconductor device provided by any one of the above-mentioned embodiments of the present application, and has the beneficial effects of the semiconductor device provided by any one of the above-mentioned embodiments of the present application.

[0155] The embodiment of the present application provides a power conversion circuit, wherein the power conversion circuit is used for one or more of current conversion, voltage conversion and power factor correction.

[0156] The power conversion circuit comprises a circuit board and at least one semiconductor device provided by any one of the above-mentioned embodiments of the present application, and the semiconductor device is electrically connected with the circuit board.

[0157] The power conversion circuit provided by any one of the above-mentioned embodiments of the present application comprises the semiconductor device provided by any one of the above-mentioned embodiments of the present application, and has the beneficial effects of the semiconductor device provided by any one of the above-mentioned embodiments of the present application.

[0158] The embodiment of the present application provides a vehicle, wherein the vehicle comprises a load and the power conversion circuit provided by any one of the above-mentioned embodiments of the present application, and the power conversion circuit is used for converting AC into DC, converting AC into AC, converting DC into DC or converting DC into AC and then inputting to the load.

[0159] The vehicle provided by any one of the above-mentioned embodiments of the present application comprises the power conversion circuit provided by any one of the above-mentioned embodiments of the present application, and the power conversion circuit provided by any one of the above-mentioned embodiments of the present application comprises the semiconductor device provided by any one of the above-mentioned embodiments of the present application, so the vehicle provided by any one of the above-mentioned embodiments of the present application has the beneficial effects of the semiconductor device provided by any one of the above-mentioned embodiments of the present application.

[0160] It should be understood that the various forms of flow shown above can be used to reorder, add or delete steps. For example, each step described in the present application can be executed in parallel, sequentially or in a different order, as long as the desired results of the technical solutions of the present application can be achieved, which is not limited herein.

[0161] The above-mentioned specific embodiments do not constitute a limitation on the protection scope of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent replacement and improvement within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A semi-insulating silicon carbide epitaxial wafer, characterized in that: include: substrate; at least one semi-insulating silicon carbide epitaxial layer located on one side of the substrate; A first epitaxial layer is located on a side of the at least one semi-insulating silicon carbide epitaxial layer away from the substrate.

2. The semi-insulating silicon carbide epitaxial wafer according to claim 1, characterized in that: The semi-insulating silicon carbide epitaxial wafer includes at least two semi-insulating silicon carbide epitaxial layers; the semi-insulating silicon carbide epitaxial wafer also includes: a second epitaxial layer; The second epitaxial layer is located between adjacent semi-insulating silicon carbide epitaxial layers.

3. The semi-insulating silicon carbide epitaxial wafer according to claim 1 or 2, characterized in that: The substrate includes a silicon substrate, and the semi-insulating silicon carbide epitaxial wafer includes a semi-insulating 3C-SiC epitaxial layer; or the substrate includes a 6H-SiC substrate, and the semi-insulating silicon carbide epitaxial layer includes a semi-insulating 4H-SiC epitaxial layer; or the substrate includes a 3C-SiC substrate, and the semi-insulating silicon carbide epitaxial layer includes a semi-insulating 4H-SiC epitaxial layer; or the substrate includes a 4H-SiC substrate, and the semi-insulating silicon carbide epitaxial layer includes a semi-insulating 3C-SiC epitaxial layer.

4. A method for preparing a semi-insulating silicon carbide epitaxial wafer, characterized in that: include: providing a substrate; forming at least one semi-insulating silicon carbide epitaxial layer on one side of the substrate; A first epitaxial layer is formed on a side of the at least one semi-insulating silicon carbide epitaxial layer away from the substrate.

5. The method for preparing a semi-insulating silicon carbide epitaxial wafer according to claim 4, wherein: At least one semi-insulating silicon carbide epitaxial layer is formed on one side of the substrate, comprising: A vanadium-containing compound or an iron-containing compound is used as a doping source, and at least one semi-insulating silicon carbide epitaxial layer is formed on one side of the substrate by using any one of chemical vapor deposition, physical vapor deposition, pulsed laser deposition, atomic layer deposition or molecular beam epitaxy processes.

6. The method for preparing a semi-insulating silicon carbide epitaxial wafer according to claim 4 or 5, characterized in that: At least one semi-insulating silicon carbide epitaxial layer is formed on one side of the substrate, comprising: forming a semi-insulating silicon carbide epitaxial layer on one side of the substrate; At least once, a second epitaxial layer is formed on a side of the semi-insulating silicon carbide epitaxial layer away from the substrate; and another layer of the semi-insulating silicon carbide epitaxial layer is formed on a side of the second epitaxial layer away from the substrate.

7. The method for preparing a semi-insulating silicon carbide epitaxial wafer according to claim 4 or 5, characterized in that: At least one semi-insulating silicon carbide epitaxial layer is formed on one side of the substrate, comprising: At least one semi-insulating 3C-SiC epitaxial layer is formed on one side of a silicon substrate; alternatively, at least one semi-insulating 4H-SiC epitaxial layer is formed on one side of a 6H-SiC substrate; alternatively, at least one semi-insulating 4H-SiC epitaxial layer is formed on one side of a 3C-SiC substrate; alternatively, at least one semi-insulating 3C-SiC epitaxial layer is formed on one side of a 4H-SiC substrate.

8. A semiconductor device, characterized in that: include: A semiconductor body; the semiconductor body includes a first surface and a second surface arranged opposite to each other, the semiconductor body also including a substrate, a first semi-insulating silicon carbide epitaxial layer, a first epitaxial layer, a well region, and a first region, the substrate is located on the second surface, the first semi-insulating silicon carbide epitaxial layer is located on a side of the substrate away from the second surface, the first epitaxial layer is located on a side of the first semi-insulating silicon carbide epitaxial layer away from the second surface, the well region is located on a side of the first epitaxial layer away from the second surface, and the first region is located on a side of the well region away from the second surface and is located on the first surface; the semiconductor body also includes a first insulating layer, the first insulating layer being located on the first surface or extending from the first surface into the semiconductor body; a gate located on a side of the first insulating layer away from the semiconductor body; a second insulating layer located on a side of the gate away from the semiconductor body; a vertical projection of the second insulating layer on the first surface covering a vertical projection of the gate on the first surface; a source electrode located on the first surface; A drain is located on the second surface.

9. A method for preparing a semiconductor device, characterized in that: include: A semiconductor body is provided; the semiconductor body includes a first surface and a second surface arranged opposite to each other, the semiconductor body further including a substrate, a first semi-insulating silicon carbide epitaxial layer, a first epitaxial layer, a well region, and a first region, the substrate being located on the second surface, the first semi-insulating silicon carbide epitaxial layer being located on a side of the substrate away from the second surface, the first epitaxial layer being located on a side of the first semi-insulating silicon carbide epitaxial layer away from the second surface, the well region being located on a side of the first epitaxial layer away from the second surface, and the first region being located on a side of the well region away from the second surface and located on the first surface; the semiconductor body further includes a first insulating layer, the first insulating layer being located on the first surface or extending from the first surface into the semiconductor body; forming a gate on a side of the first insulating layer away from the semiconductor body; forming a second insulating layer on a side of the gate away from the semiconductor body; a vertical projection of the second insulating layer on the first surface covers a vertical projection of the gate on the first surface; forming a source electrode on the first surface; A drain electrode is formed on the second surface.

10. A semiconductor device, characterized in that: include: A semiconductor body; the semiconductor body includes a first surface and a second surface arranged opposite to each other, the semiconductor body further including a substrate, a first semi-insulating silicon carbide epitaxial layer, a first epitaxial layer, and a first region, the substrate being located on the second surface, the first semi-insulating silicon carbide epitaxial layer being located on a side of the substrate away from the second surface, the first epitaxial layer being located on a side of the first semi-insulating silicon carbide epitaxial layer away from the second surface, and the first region being located on a side of the first epitaxial layer away from the second surface and located on the first surface; an anode located on the first surface; A cathode is located on the second surface.

11. The semiconductor device according to claim 8 or 10, characterized in that The semiconductor body further includes: a second semi-insulating silicon carbide epitaxial layer and a second epitaxial layer; The second semi-insulating silicon carbide epitaxial layer and the second epitaxial layer are located between the substrate and the first semi-insulating silicon carbide epitaxial layer, the second semi-insulating silicon carbide epitaxial layer is located on a side of the substrate away from the second surface, and the second epitaxial layer is located on a side of the second semi-insulating silicon carbide epitaxial layer away from the second surface.

12. A method for preparing a semiconductor device, characterized in that: include: A semiconductor body is provided; the semiconductor body includes a first surface and a second surface arranged opposite to each other, and the semiconductor body further includes a substrate, a first semi-insulating silicon carbide epitaxial layer, a first epitaxial layer, and a first region, wherein the substrate is located on the second surface, the first semi-insulating silicon carbide epitaxial layer is located on a side of the substrate away from the second surface, the first epitaxial layer is located on a side of the first semi-insulating silicon carbide epitaxial layer away from the second surface, and the first region is located on a side of the first epitaxial layer away from the second surface and is located on the first surface; forming an anode on the first surface; A cathode is formed on the second surface.

13. The method for preparing a semiconductor device according to claim 9 or 12, wherein: Provide a semiconductor body, including: A vanadium-containing compound or an iron-containing compound is used as a doping source, and any one of chemical vapor deposition, physical vapor deposition, pulsed laser deposition, atomic layer deposition or molecular beam epitaxy processes is used to form the first semi-insulating silicon carbide epitaxial layer on a side of the substrate away from the second surface.

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