22 results about "Sidewall roughness" patented technology

The invention discloses a silicon-based micro-channel plate (MCP) structure and a manufacturing method thereof, relates to the technical field of semiconductor device manufacturing, and aims to solve the problems of poor high temperature resistance, insufficient etching precision, film layer quality defect and process synergy deficiency of a traditional glass-based / organic-based MCP. An 8-inch N-type monocrystalline silicon wafer is adopted in the structure, the thickness of the N-type monocrystalline silicon wafer is (250-350) + / -25 microns, micropores of 3-10 microns are evenly distributed, the hole pitch is 7-22 microns, the inclination angle is 6-12 degrees, the side wall roughness is smaller than or equal to 50 nm, the perpendicularity deviation is smaller than or equal to + / -0.5 degrees, an AlO or AlO / HfO / AlO electron multiplication layer with the thickness of 10-30 nm is prepared on the inner wall of a channel through ALD, and a Cr / Ni electrode with the thickness of 50-80 nm is plated on the surface. According to the method, the OES is used for monitoring SiFs in real time. According to the invention, the double targets of < = 30% of 1kg impact fracture rate and stable electron multiplication gain are achieved, the tolerable temperature reaches 800 DEG C, the secondary electron emission efficiency is improved by 25%, the production efficiency is improved by 20%, the cost is reduced by 15%, and the method is suitable for the high-sensitivity detection fields of night vision imaging, particle detection and the like.

The invention provides an etching method and semiconductor process equipment, relates to the technical field of semiconductors, and is designed for solving the problem that the roughness of the side wall of a deep groove structure obtained by etching through an etching process provided by the related technology is large. The etching method comprises the following steps: providing a substrate; performing a photoetching step and a first etching step on the substrate to form a first groove in the substrate; performing normal-temperature oxidation to form a protection layer covering the first groove; removing the protection layer on the bottom wall of the first groove; and performing a second etching step on the first groove to form a second groove on the substrate. The invention can reduce the roughness of the side wall.

The invention discloses lithium niobate with high anisotropy and a smooth side wall and a preparation method of the lithium niobate, and belongs to the technical field of semiconductor processes. The preparation method comprises the following steps: by adopting typical reaction etching, the advantage of higher selectivity during reaction ion beam etching is reserved; adding a sacrificial mask SOH to isolate the top and sidewalls of the lithium niobate layer having the initial tapered profile; by increasing the thickness of the top metal hard mask, the mask budget of the top metal hard mask in subsequent etching is improved; and finally, etching the side wall comprising the redeposition layer and the conical lithium niobate structure with the metal seeds by adopting an ion beam, and finally cooperatively realizing a vertical side wall shape and a smooth side wall surface through zero-angle etching treatment, so as to obtain the lithium niobate with high anisotropy and a smooth side wall. According to the method, the separation of the top area and the side wall area of the lithium niobate is realized, the side wall roughness problem after the heavy deposition layer is removed is repaired, and the lithium niobate with high anisotropy and smooth side wall is obtained.

The application discloses a semiconductor structure and a manufacturing method thereof. The method comprises the following steps: forming a functional layer and a hard mask pattern on a substrate; performing a first treatment on the sidewall of the hard mask pattern to remove the protruding part on the sidewall of the hard mask pattern to reduce the sidewall roughness, and forming a polymer layer on the sidewall of the hard mask pattern for protection; etching the functional layer through the hard mask pattern to form a waveguide pattern; performing a second treatment on the sidewall of the waveguide pattern with the hard mask pattern, wherein the second treatment comprises a treatment step and a passivation step which are alternately cycled, the treatment step is used for removing the protruding part on the sidewall of the waveguide pattern to reduce the sidewall roughness, and the passivation step is used for surface passivation of the sidewall of the waveguide pattern for protection; and performing a third treatment on the sidewall of the waveguide pattern after removing the hard mask pattern to further reduce the sidewall roughness. The application can significantly improve the smoothness of the sidewall of the waveguide pattern and improve the key performance of the device.

A system for measuring roughness of a core sidewall of an optical waveguide based on mode excitation is provided, in which an optical waveguide to be measured is arranged between a few-mode long-period fiber grating and an optical power meter; the laser beam is incident on the optical waveguide to be measured after passing through the few-mode long-period fiber grating, and then is incident on the optical power meter after being subjected to a scattering loss caused by the roughness of the core sidewall of the optical waveguide to be measured; and the processor is configured to calculate an equivalent value of the roughness of the core sidewall according to the output power detected by the optical power meter, the output modes of the few-mode long-period fiber grating and the mode of the optical waveguide to be measured.

The invention relates to a method for sidewall roughness control and structural defect reduction of features on a substrate. The method includes adjusting a tilt angle of the particle beam to perform an angled particle beam etch of at least one sidewall of the feature. The techniques enable improved sidewall roughness control and structural defect reduction in various applications such as semiconductor fabrication. Methods for pattern improvement, cyclic surface conditioning, and etching feature sidewalls are also disclosed.

The invention provides an optimization processing method for roughness of a side wall of a glass blind groove. The optimization processing method comprises the following steps: S1, carrying out first-time laser-induced modification on a glass substrate according to a track I by adopting first laser; s2, second laser is adopted for conducting second-time laser-induced modification on the modified glass substrate according to a second track, and the second track is located on the outer side of the first track, a plurality of second ablation points formed by modifying the second laser on the track II on the glass substrate and a plurality of first ablation points formed by modifying the first laser on the track I on the glass substrate are arranged in a staggered manner; and S3, carrying out chemical corrosion treatment on the glass substrate subjected to laser-induced modification twice. According to the method, on the basis of the first laser-induced modification, the modified glass substrate is subjected to the second laser-induced modification by using the second laser, so that the roughness Ra of the side wall of the glass blind groove can reach 100 nm or below, the glass micropore forming quality is improved, and the signal transmission performance of the glass substrate and the CPO packaging stability are also improved.

The invention discloses a method for improving the roughness of an InAs / GaSb superlattice etching side wall. A to-be-etched InAs / GaSb superlattice sample and at least one solid indium-containing auxiliary source dummy wafer are jointly placed in an etching reaction cavity for etching. According to the method, an existing mainstream chlorine-based dry etching platform does not need to be changed, only the solid indium-containing auxiliary source dummy wafer needs to be added in the cavity, additional complex steps are not introduced, and the solid indium-containing auxiliary source dummy wafer can be easily integrated into an existing production line; by introducing the external indium source to actively modify the side wall, the problem of etching non-uniformity caused by material difference is fundamentally compensated, the effect is better than that of simply optimizing etching parameters, the quality of the side wall is remarkably improved, the dark current of the infrared detector is remarkably reduced, and the reliability and the yield of the device are improved. The method is suitable for various mesa etching processes of infrared detectors based on InAs / GaSb superlattices, and has wide applicability.

This invention belongs to the field of quality inspection technology, and provides a surface etching quality inspection system and method for circuit boards. The method includes: scanning the entire etched circuit board, extracting features such as sidewall roughness and flatness, and establishing a target feature parameter set containing planar roughness data; performing defect feature matching based on the target feature parameter set to obtain effective segments of sawtooth defects, extracting defect geometric features and signal insertion loss features, and constructing a quantitative mapping model; triggering phase shift detection based on the insertion loss prediction value output by the quantitative mapping model, and constructing a defect detection boundary by combining historical detection data; analyzing the distribution bias of defect parameters within the defect detection boundary, and predicting the direction of defect over-standard evolution. The system includes: a feature extraction module, a mapping establishment module, a boundary recognition module, and an evolution analysis module. This invention is beneficial for improving the etching quality of circuit boards and is applicable to circuit board etching quality inspection scenarios.

The embodiment of the invention provides a Bragg grating manufacturing method which comprises the following steps: etching a transition material on a substrate to form a periodic fluctuating structure on the substrate, generating an upper cladding layer on the periodic fluctuating structure through chemical vapor deposition, and generating a grating material on the upper cladding layer through chemical vapor deposition to form a Bragg grating. Through the method and the device, the problems that certain process errors exist between an actual Bragg grating structure and an expected design structure in related technologies, and unpredictable influence on the performance of the Bragg grating is generated are solved, so that the effects that the influence caused by the roughness of the side wall is smaller, the requirement on the etching process precision is lower, and the manufacturing cost is lower are achieved. And the manufactured Bragg grating is more stable in performance.

This invention relates to a method and system for fabricating an ultra-small AWG chip, comprising: using ICP-VD technology on a silicon substrate to controllably grow a low-stress, low-optical-absorption silicon nitride thin film by adjusting plasma power and gas flow rate; covering the silicon nitride thin film with a hybrid mask, and determining a reactive ion etching combination with a primary etching gas and an auxiliary passivation gas according to a target volume ratio; etching the silicon nitride thin film based on the reactive ion etching combination to form a silicon nitride waveguide structure with a sidewall roughness less than a preset roughness threshold; adjusting the thickness and width of the waveguide to achieve a design goal of ultra-thin and ultra-wide waveguide compatible with single-mode transmission characteristics and low bending loss, and designing the bending transition section of the waveguide as a gradually curved structure by transforming optical principles; integrating the designed waveguide into the AWG chip in a preset array configuration, and using a Rowland circle overlapping lithography to compress the overlapping area between the input and output waveguides in the array.

The invention relates to the technical field of micro-nano machining and integrated photonics, in particular to a nanoimprint silicon template optimization method for an integrated photonic circuit, and aims to solve the problem that the optical loss of a copied photonic device is large due to the fact that the roughness of the side wall of an existing nanoimprint silicon template is high. In order to solve the problem that the service life of the template is influenced by the performance such as the central wavelength of the device due to the change of waveguide line width caused by the loss of the template after multiple times of imprinting, various optimization schemes which can be implemented independently or in a combined manner are provided; according to the scheme, the method comprises the steps of hydrogen annealing smoothing based on surface atom migration, smoothing based on thermal oxidation and hot reflux, fine smoothing based on cyclic thermal oxidation and wet etching, and conformal thin film deposition based on LPCVD / ALD. The invention further provides the high-smoothness and high-durability functionalized nanoimprint template prepared through the method and application of the high-smoothness and high-durability functionalized nanoimprint template to preparation of low-loss integrated photonic devices. The performance of the imprinting photonic device can be remarkably improved, and the service life of the template can be remarkably prolonged.

The invention relates to a microminiature AWG chip manufacturing method and system, and the method comprises the steps: employing an ICPCVD technology on a silicon substrate, and carrying out the controllable growth of a low-stress and low-optical-absorption silicon nitride film through adjusting the plasma power and gas flow; covering the mixed mask on the silicon nitride film, and determining a reactive ion etching combination which takes a main etching gas as an auxiliary passivation gas according to a target volume ratio; the silicon nitride thin film is etched based on the reactive ion etching combination, and a silicon nitride waveguide structure with the side wall roughness smaller than a preset roughness threshold value is formed; the thickness and width of the waveguide are adjusted under the design target of the ultrathin and ultra-wide waveguide compatible with the single-mode transmission characteristic and the low bending loss, and the bending transition section of the waveguide is designed into a gradually-changed bending structure by changing the optical principle; and integrating the designed waveguides in an AWG chip according to a preset array form, and compressing an overlapping region between the input waveguide and the output waveguide in the array by adopting Rowland circle overlapping layout.

The application discloses a quantum computing chip based on a vertical micro-lens, a system on a chip and a simulator correction method thereof, a vertical micro-lens structure with roughness less than 5nm can be formed by smoothing the sidewall of a deep etching vertical structure, which can greatly reduce the loss of light irradiation on the sidewall interface of a silicon-based optical device, a quantum computing chip is developed on a silicon wafer, another optical computing chip structure other than macroscopic space optics and silicon-based optoelectronics is realized, and the process is fully compatible with advanced packaging processes, so that photoelectric wafer-level system integration of sensing, storage and calculation can be realized. For the system on a chip of the integrated quantum computing chip, the integrated circuit chip (and the optical sensing chip), the crosstalk, loss and delay of the TSV transmission signal are reduced through the vertical micro-lens technology, and the indirect measurement of the sidewall roughness is realized through the Fabry-Perot interference, and then the ideal system on a chip simulator is corrected, so that the simulation result of the simulator is closer to the actual measurement result of the system on a chip.

The application belongs to the technical field of mechanical manufacturing, and discloses a process method for improving flatness of laser cutting processing. The method immerses a wafer in a specific electrolyte, applies an electrochemical bias voltage at the same time of pulse laser irradiation, and makes a molten area realize in-situ trimming under the effect of rapid cooling and anode flattening. The electrolyte has high light transmittance, adaptive conductivity and selective dissolving capacity, and cooperates with nanosecond / picosecond laser parameters and synchronous electrochemical control to obtain a high-quality cutting structure with a side wall roughness Ra<50nm and no significant burr and recast layer. The application provides an integrated process method for simultaneously implementing laser cutting and electrochemical polishing in a specific electrolyte environment, cooperatively regulates molten pool dynamics and interfacial electrochemical reaction through multiple physical fields, fundamentally solves the technical problem that burrs and recast layers are difficult to suppress in laser cutting of high-thermal-conductivity metals, and provides key process support for high-density three-dimensional packaging and heterogeneous integrated manufacturing.

This invention belongs to the field of through-silicon via (TSV) inspection technology, specifically relating to a probe for detecting the geometric parameters of the inner wall of a TSV. The probe includes a probe rod and a probe head; the aspect ratio of the probe rod is 10~50:1; the probe head includes a hemispherical portion and a tip, the hemispherical portion and the tip being integrally connected, with the tip of the tip located away from the hemispherical portion; the hemispherical portion is integrally connected to the probe rod, and the angle between the tip of the tip and the axis of the probe rod is 70°~110°; the radius of curvature of the tip is 10nm~50nm, and both the probe rod and the probe head are made of tungsten. The probe of this invention can meet the measurement requirements for critical dimensions and sidewall roughness of TSVs with an aspect ratio greater than 10:1.

The application relates to the technical field of etching process control, and discloses a planar optical element scattering budget gated acceptance method and system, computer equipment and a storage medium. The method comprises the following steps: acquiring a microstructure sidewall roughness parameter and a surface roughness parameter of a target planar optical element; acquiring a multi-component identity of an etching cavity; inputting the roughness parameter and the multi-component identity into a multi-source heterogeneity scattering budget model to calculate an expected scattering loss value; calculating a preset scattering loss threshold value according to a microstructure aspect ratio and a material absorption coefficient; comparing the expected scattering loss value with the threshold value to output a qualified or unqualified determination result; when the determination result is unqualified, the expected scattering loss value is decomposed into a fixed effect component and a plurality of independent random effect components through variance decomposition, and a maintenance suggestion for the corresponding component is generated. The application realizes accurate prediction of scattering loss and component-level tracing of process abnormalities, and improves acceptance accuracy and abnormal troubleshooting efficiency.

The embodiment of the application discloses a metal wire manufacturing method and a semiconductor structure, which comprises the following steps: forming a metal layer of a ruthenium material on a substrate; performing first etching on the metal layer to form a groove intermediate structure; depositing a carbon-based protective layer on the inner wall of the groove intermediate structure; performing second etching on the carbon-based protective layer on the bottom of the groove intermediate structure to remove the carbon-based protective layer, and performing oxidation on the exposed surface of the ruthenium material to form a ruthenium dioxide surface layer; performing third etching on the ruthenium dioxide surface layer to remove the ruthenium dioxide surface layer and expose the surface of the underlying ruthenium material, so that the first etching is performed again; the process of the first etching, the deposition of the carbon-based protective layer, the second etching and the third etching is repeatedly performed in sequence until the groove completion structure and the metal wires divided by the groove completion structure are formed; and the groove sidewall is cleaned. The embodiment of the application can improve the sidewall roughness difference problem from the source in the etching process, reduce the risk of short circuit or open circuit, and realize lower resistance and interconnection stability.

The application discloses a preparation method of a ridge waveguide structure and the ridge waveguide structure, and comprises the following steps: forming a first waveguide cladding layer, a waveguide layer and a hard mask on a substrate; etching the waveguide layer to form a ridge waveguide pattern through the hard mask; using first hydrogen radicals to perform first processing on the sidewall of the ridge waveguide pattern with the hard mask, so as to remove first protruding parts on the sidewall; using first hydroxyl radicals to perform second processing on the sidewall, so as to perform surface passivation protection on the sidewall; alternately performing the first processing and the second processing for multiple times, so as to reduce the sidewall roughness; removing the hard mask; using second hydrogen radicals and second hydroxyl radicals to perform third processing on the exposed surface of the ridge waveguide pattern, so as to reduce the surface roughness; and forming a second waveguide cladding layer for covering the ridge waveguide pattern. The application can significantly improve the smoothness of the surface of the ridge waveguide pattern, thereby improving the key performance of a device.

The invention belongs to the technical field of machine manufacturing, and discloses a technological method for improving laser cutting machining flatness. According to the method, a wafer is immersed in a specific electrolyte, and electrochemical bias voltage is applied while pulse laser irradiation is carried out, so that in-situ finishing of a fusion area is realized under the action of rapid cooling and anode leveling; the electrolyte has high light transmittance, adaptive conductivity and selective dissolving capacity, and can be matched with nanosecond / picosecond laser parameters and synchronous electrochemical control to obtain a high-quality cutting structure of which the side wall roughness Ra is less than 50nm and which is free from obvious burrs and recast layers. The invention provides an integrated process method for synchronously implementing laser cutting and electrochemical polishing in a specific electrolyte environment, and the technical problem that burrs and a recast layer are difficult to restrain in laser cutting of high-thermal-conductivity metal is fundamentally solved by cooperatively regulating and controlling molten pool dynamics and an interface electrochemical reaction through multiple physical fields. And a key process support is provided for high-density three-dimensional packaging and heterogeneous integrated manufacturing.

This invention relates to a method for controlling the sidewall roughness and reducing structural defects of feature areas on a substrate. The method includes adjusting the inclination angle of a particle beam for oblique incidence particle beam etching of at least one sidewall of a feature area. This technique enables improved control of sidewall roughness and reduction of structural defects in various applications such as semiconductor manufacturing. Methods for pattern improvement, cyclic surface preparation, and etching the sidewalls of feature areas are also disclosed.

The invention provides an etching control method and related equipment for a low-loss waveguide of a laser chip, and the method comprises the steps: synchronously forming a main waveguide ridge and monitoring ridges with different widths on a semiconductor substrate through etching, and enabling the monitoring ridges to comprise a narrow-width monitoring ridge and a wide-width monitoring ridge; in the etching process, optical excitation is applied to the monitoring ridges to collect scattered light intensity signals, difference processing is carried out on scattered light intensity of the narrow-width monitoring ridges and scattered light intensity of the wide-width monitoring ridges to judge the roughness of the side wall, and when the roughness of the side wall deviates from a preset interval, etching process parameters are adjusted; after the passivation layer is deposited, optical excitation is applied to the monitoring ridges to collect guided mode light intensity signals, the guided mode light intensity of the narrow-width monitoring ridge and the guided mode light intensity of the wide-width monitoring ridge are compared to judge the coverage uniformity of the passivation layer, and when the coverage uniformity deviates from a preset threshold value, passivation process parameters are adjusted. In-situ monitoring of the roughness of the side wall and the uniformity of the passivation layer and real-time adjustment of process parameters are achieved, and the problem that the batch consistency is poor due to the fact that real-time feedback cannot be achieved through off-line detection is solved.