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Photolithography method capable of reducing line roughness

A roughness and line technology, applied in the field of semiconductor integrated circuit manufacturing, can solve the problems of unobtainable lines, insufficient height, loss, etc., and achieve the effect of reducing roughness, improving stability, and reducing fluctuations

Inactive Publication Date: 2014-05-07
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The thinner photoresist can expose smaller lines. However, due to the insufficient selectivity of the etching process, such thin photoresist will often be lost early in the etching process, thus failing to obtain the desired lines, and there is a serious line roughness problem

Method used

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  • Photolithography method capable of reducing line roughness
  • Photolithography method capable of reducing line roughness
  • Photolithography method capable of reducing line roughness

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Embodiment Construction

[0020] The features and technical effects of the technical solution of the present invention will be described in detail below with reference to the accompanying drawings and in combination with exemplary embodiments. It should be pointed out that similar reference numerals represent similar structures, and the terms "first", "second", "upper", "lower", "thick", "thin" and the like used in this application can be used for Modify various device structures. These modifications do not imply a spatial, sequential or hierarchical relationship of the modified device structures unless specifically stated.

[0021] Reference attached figure 1 , shows a schematic diagram of an e-beam lithography layout for small linewidth features such as gate electrode layers, local interconnect layers, etc. In the present invention, the fine pattern FP is defined as a pattern that is beyond the capability of ordinary optical exposure and needs to be exposed by electron beams, and lines with a patte...

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Abstract

The invention discloses a photolithography method capable of reducing line roughness. The method comprises the following steps: forming a structural material layer and hard mask layers on a substrate; forming electronic beam photoresist on the hard mask layers, then forming electronic beam photoresist graphics by executing electronic beam overexposure, wherein the exposure dose is increased so as to improve the roughness; taking the electronic beam photoresist graphics as the mask, forming hard mask graphics by etching; taking the hard mask graphics as the mask, and etching the structural material layer so as to formed the needed fine lines. In this method, a plurality of hard mask layers made of different materials is adopted and photolithography conditions are reasonably adjusted at the same time so as to prevent the roughness degree of the sidewall of the electronic beam photoresist from being transmitted to the structural material layer under the hard mask layers, thus the line roughness is effectively reduced, the technology stability is improved, and the fluctuation of device performance is reduced.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, and more specifically, relates to a photolithographic method for reducing line roughness by using electron beam overexposure technology. Background technique [0002] With the gradual reduction of VLSI feature size, the technical limit of ordinary optical exposure has come after entering the 22nm technology generation in the manufacturing method of semiconductor devices. At present, after the 45nm process node, i193nm immersion lithography technology combined with double exposure and double etching technology is generally used to prepare smaller lines. Fine patterning at nodes below 22nm typically requires exposure and lithography using e-beam or EUV. [0003] Regarding EUV lithography technology, it is still in the research and development stage, and there are still several key technologies that need to be overcome and improved, and it cannot be applied to large-sca...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G03F7/20G03F1/80H01L21/027H01L21/033
Inventor 孟令款贺晓彬李春龙
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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