3D IC testing apparatus

Abstract

A three dimensional (3D) integrated circuit (IC) testing apparatus comprises a plurality of connection devices. When a device under test (DUT) (such as an interposer or a 3D IC) formed by a plurality of 3D dies operates in a testing mode, the 3D IC testing apparatus is coupled to the DUT via a variety of interface channels (such as probes). The connection devices and a variety of through silicon vias (TSVs) in the DUT form a TSV chain so that electrical characteristics of the variety of TSVs can be tested all at once.

Description

technical field [0001] The invention relates to the field of semiconductors, and more specifically, to a 3D IC testing device. Background technique [0002] With the development of semiconductor technology, three-dimensional (3D) integrated circuits (ICs) have become an effective option for further reducing the physical size of semiconductor chips. In semiconductor chip-based 3D ICs, active circuits are fabricated on separate wafers and each wafer die is stacked on top of another wafer die using pick-and-place techniques. on top. Higher densities can be achieved by using 3D ICs. In addition, 3D ICs enable smaller form factors, cost-effectiveness, enhanced performance, and lower power consumption. [0003] In the development process of 3D IC, an intermediate stage called 2.5D IC was produced. In a 2.5D IC, there may be multiple dies including active circuitry and multiple interposers including through silicon vias (TSVs). Unlike 3D ICs, in 2.5D ICs various dies including...

AI Technical Summary

Problems solved by technology

When TSVs are formed before the different layers are stacked together, defects can arise due to operational variations in the 3D IC manufacturing process

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