Machine allocation of IC test processor and process for making the same

A technology for testing processors and machines, which is applied in the direction of electronic circuit testing, single semiconductor device testing, semiconductor/solid-state device testing/measurement, etc., and can solve problems affecting the execution efficiency of IC test processors and interruption of work in test areas, etc.

Inactive Publication Date: 2003-12-31
TASK TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Such a simple and direct IC chip delivery process is the key to the production efficiency of the entire machine, because on the machine delivery line of the IC test handler, there is often a supply of the test area for replacing the IC tray (TRAY). The situation...

Method used

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  • Machine allocation of IC test processor and process for making the same
  • Machine allocation of IC test processor and process for making the same
  • Machine allocation of IC test processor and process for making the same

Examples

Experimental program
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Embodiment Construction

[0054] Please refer to figure 1 The main structure shown is a small machine 1, and the machine 1 is equipped with a stacking feeding buffer part 2, an empty tray dispatching mechanism 5, an empty IC tray dispatching mechanism, a double IC delivery arm 31 in the testing part, and a testing part Double IC delivery arm 32, reciprocating transport temporary storage disk, IC test area 7, IC completion test placement area 8 and other mechanisms, its features are:

[0055]Stacked feeding buffer: located on the far side of the machine, it is a stacked feeding tray filled with ICs to be tested. Each feeding tray can be used for lifting and conveying in the Z-axis direction; and the bottom feeding tray can be moved by Y The axis transmission mechanism moves in the Y-axis direction; the empty IC tray dispatching mechanism; it is composed of a base of the X-axis transmission mechanism and its cantilever. The cantilever is equipped with a vacuum suction cup, and a central axis on the base ...

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Abstract

The present invention is test bench configuration and measurement process for IC test. The test bench includes material stacking and feed buffering area for stacking ICs to be tested; empty IC tray dispatching mechanism for sucking empty tray for concentration in the empty IC tray area; double-IC conveying arm with double sucking heads to suck one pair of ICs; one pair of alternately conveyed temporary storing trays for conveying ICs to IC test area for continuous test; and tested IC setting area. In the test bench, all tested ICs are set based on their parameters. The present invention has high efficiency, small covered area and short processing path.

Description

technical field [0001] The invention relates to a machine configuration and processing flow of an IC test processor, in particular to a machine used for IC test operation program processing, and the IC to be tested is sent to the test head to perform the test and after the test is completed. According to the operation mode and configuration mode of each mechanism required by the IC test results, classification and placement procedures, the configuration is most in line with work efficiency, so as to increase the efficiency of operation execution. Background technique [0002] In the whole machine processing flow of IC test handler (IC Handler), the most important point is: how to maintain the test fluency of IC test head (IC TEST HEAD) as much as possible, without interrupting the operation of testing IC. affect overall performance. General IC test handlers do not focus on the smoothness of the flow of the IC on the machine, and often only use a vacuum conveying arm to suck...

Claims

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Application Information

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IPC IPC(8): G01R31/28H01L21/66
Inventor 蔡译庆
Owner TASK TECH
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