IC (integrated circuit) testing device and method

Abstract

The invention discloses an IC (integrated circuit) testing device and method. The device comprises a controller, a socket, N testing modules, N relays, an analog switch group and a communication circuit, a second end of the analog switch group is connected with the socket, a control end of the analog switch group is connected with the controller, L-level multi-input analog switches are cascaded to form the analog switch group, the analog switch group is used for selecting corresponding pins of a chip to be tested to connect with corresponding testing modules according to control of the controller, a first end of the communication circuit is connected with the controller, the other end of the communication circuit is connected with the socket, and the communication circuit is used for establishing communication between the controller and the socket. According to the testing device, the analog switch group formed by cascade of the L-level multi-input analog switches is arranged between the N testing modules and the socket for placing chips to be tested, pins of the chips to be tested cannot be directly with the controller when the chips to be tested are tested, a plurality of controller are omitted, controller resources are greatly saved, cost of the testing device is reduced, and structures of the testing device are simplified.

Description

technical field [0001] The invention relates to the technical field of chip testing, in particular to an IC testing device and method. Background technique [0002] With the development of microelectronics technology and the continuous increase of market demand for integrated chips, IC testing devices have also followed the continuous development. At present, the integration level of integrated chips is getting higher and higher, the functions are more and more complex, the performance requirements are getting higher and higher, and the power consumption requirements are getting lower and lower, but at the same time, the lower the cost, the better. At present, the number of pins of packaged integrated chips is increasing, up to hundreds or even thousands of pins, and each pin packaged may be multiplexed with multiple functions, and sold to customers in the integrated chip In the past, integrated chip manufacturers had to perform FT tests on each integrated chip to pick out ...

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Problems solved by technology

[0003] 1) When there are many IO pins of the chip to be tested, the IO pins of the controller may not be enough, so it is possible to use multiple controllers to test the chip to be tested. It is an increase in cost. The controllers here are generally FPGA chips, single-chip microcomputers (more powerful), DSP chips or ARM chips, etc. These chips are generally more expensive, and the design of printed circuit boards may be more complicated. , leading to an increase in the cost and difficulty of PCB design; in addition, the use of multiple controllers will increase the difficulty of development, debugging and maintenance

[0004] 2) At present, the number of IO pins of most chips to be tested is increasing, and each IO pin may be a combination of multiple functions. To test all the functions of a certain IO of the chip to be tested, multiple controll

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