Engineering test method and system for storage chip and medium

Abstract

The invention provides an engineering test method and system for a storage chip and a medium, and belongs to the technical field of semiconductor packaging. The method comprises the following steps: acquiring read-write operation data, temperature data and voltage data of a storage chip in real time through a distributed sensor network, performing dimension reduction and segmentation processing on test data by using a multi-dimensional feature extraction algorithm, extracting statistical features and correlation features, inputting a fault prediction model constructed based on a deep learning algorithm, and performing fault prediction. Fault type and probability prediction is realized; and judging whether the chip has a fault by combining a preset threshold value, if the chip has the fault, accurately positioning a fault area by adopting a dynamic probe test technology, determining a fault time point and a trigger condition through time sequence analysis, and finally generating a fault diagnosis report and providing a repair suggestion. According to the invention, the accuracy and efficiency of fault detection of the storage chip can be effectively improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor packaging, in particular to an engineering test method, system and medium for a storage chip. BACKGROUND

[0002] With the rapid development of semiconductor technology, storage chips are increasingly widely used in electronic devices, and their performance and reliability directly affect the overall operation of the device. In the production and use of storage chips, engineering testing is a key link to ensure chip quality. Currently, traditional storage chip testing methods rely heavily on static parameter detection and simple functional testing, such as measuring only the basic parameters of the chip such as voltage and current, or testing the storage function of the chip through fixed read and write instructions. These methods have obvious defects: on the one hand, due to the lack of collection and analysis of dynamic data during chip operation, it is difficult to detect potential faults caused by dynamic factors such as temperature changes and voltage fluctuations; on the other hand, the fault diagnosis process mainly relies on manual experience, lacks systematicness and accuracy, resulting in low fault location efficiency and high misdiagnosis rate, which cannot meet the testing needs of modern high-performance storage chips. In addition, existing testing methods cannot analyze the causes of faults in depth, making it difficult to provide effective repair suggestions, which is not conducive to the optimization of chip performance and the improvement of production processes. Therefore, there is an urgent need for a storage chip engineering test method that can achieve multi-dimensional data collection, accurate fault prediction and positioning, and provide comprehensive fault diagnosis. SUMMARY

[0003] The purpose of the present application is to provide an engineering test method, system and medium for a storage chip. By collecting multi-dimensional data such as chip read and write, temperature, voltage, etc. through a distributed sensor network, using a multi-dimensional feature extraction algorithm to process and input into a deep learning fault prediction model, and combining threshold values to determine whether the chip is faulty. If there is a fault, use dynamic probe technology for accurate positioning, determine the fault time and trigger conditions through time series analysis, generate a visual diagnostic report and provide repair suggestions. The matching test system and computer-readable storage medium can implement this method, which can effectively improve the fault detection accuracy and test efficiency, and facilitate integrated application.

[0004] The present application provides an engineering test method for a storage chip, comprising the following steps: Obtaining test data of the storage chip, the test data including read and write operation data, temperature data and voltage data of the storage chip; Based on a pre-set multi-dimensional feature extraction algorithm, feature extraction is performed on the test data to obtain feature data of multiple dimensions; input the multi-dimensional feature data into a pre-trained fault prediction model, the fault prediction model is constructed based on a deep learning algorithm, trained by a large amount of historical test data and corresponding fault labels, and used for predicting the fault type and fault probability of the storage chip; According to the fault type and fault probability output by the fault prediction model, combined with the preset fault threshold, it is judged whether the storage chip has a fault or not; If it is judged that there is a fault, according to the fault type and internal structure information of the storage chip, a dynamic probe test technology is used to accurately locate the fault area of the storage chip; Obtain the detailed test data of the fault area, and perform timing analysis on the detailed test data to determine the specific time point and trigger condition of the fault occurrence; According to the fault type, fault area, fault occurrence time point and trigger condition, a fault diagnosis report of the storage chip is generated, and a corresponding repair suggestion is provided.

[0005] In the storage chip engineering test method described in the present application, the test data of the storage chip is obtained, including: The distributed sensor network is used to collect real-time read-write operation data, temperature data and voltage data of the storage chip under different workloads; The distributed sensor network includes temperature sensors, voltage sensors and data transmission monitoring modules deployed at key nodes of the storage chip.

[0006] In the storage chip engineering test method described in the present application, the feature extraction algorithm based on the preset multi-dimensional feature extraction algorithm is used to extract the features of the test data to obtain multi-dimensional feature data, specifically: The principal component analysis algorithm is used to reduce the dimension of the test data and remove data redundancy; The test data is segmented by the sliding window technology to capture the change trend of the data in different time windows; The statistical features including mean, variance and other statistical quantities are extracted from the test data, and the correlation features between different types of test data are extracted.

[0007] In the storage chip engineering test method described in the present application, the training process of the fault prediction model includes: The cross-validation method is used to divide the large amount of historical test data into a training set, a validation set and a test set; The accuracy and generalization ability of the fault prediction model are optimized by adjusting the hyperparameters of the deep learning algorithm; The hyperparameters at least include the number of layers, the number of neurons and the learning rate of the deep learning network.

[0008] In the engineering test method of the storage chip, the fault type and the fault probability output by the fault prediction model are combined with the preset fault threshold to determine whether the storage chip has a fault, and the determination is specifically as follows: Obtaining the fault probability of the same fault type within a preset time; Comparing the fault probability with the preset fault threshold and performing counting processing; If the fault probability is greater than or equal to the preset fault threshold for three consecutive times, it is determined that the storage chip has a fault, so as to reduce the misjudgment rate.

[0009] In the engineering test method of the storage chip, the dynamic probe test technology is used to accurately locate the fault area of the storage chip, and the specific process is as follows: The dynamic probe test technology is based on the preliminary fault range output by the fault prediction model, and first performs area-level scanning, and then gradually narrows down to block-level, page-level, and finally the smallest storage unit block; By comparing the real-time electrical characteristic data obtained by probe scanning with the standard parameters in the address mapping table, the physical address of the abnormal storage unit is identified; The boundary scanning technology is used to verify the positioning result, and the boundary range of the fault unit is further confirmed by injecting test vectors into adjacent normal units.

[0010] In the engineering test method of the storage chip, the fault diagnosis report of the storage chip is generated, which includes: The heat map is used to intuitively show the distribution density of the fault area in the physical layout of the chip, and the time sequence diagram is used to present the correlation between the fault occurrence time point and the system operation; The box plot is used to compare the statistical differences of key parameters such as voltage fluctuation range and temperature extreme value at the fault time and in the normal state; The association rule mining technology is used to automatically label the fault triggering condition, and the causal relationship chain between the abnormal parameter combination and the fault type is displayed in the form of a decision tree in the report.

[0011] In a second aspect, the application provides an engineering test system for a storage chip, which comprises a memory and a processor, wherein the memory comprises a program of an engineering test method for a storage chip, and the program of the engineering test method for a storage chip is executed by the processor to realize the following steps: Obtaining test data of the storage chip, wherein the test data comprises read-write operation data, temperature data and voltage data of the storage chip; Based on a preset multi-dimensional feature extraction algorithm, the test data is subjected to feature extraction to obtain multi-dimensional feature data; input the plurality of dimensional feature data into a pre-trained fault prediction model, the fault prediction model being constructed based on a deep learning algorithm and trained by a large amount of historical test data and corresponding fault labels, and used for predicting a fault type and a fault probability of the storage chip; determine whether the storage chip has a fault according to the fault type and the fault probability output by the fault prediction model and in combination with a preset fault threshold; if it is determined that there is a fault, accurately locate a fault region of the storage chip by using a dynamic probe test technology according to the fault type and internal structure information of the storage chip; obtain detailed test data of the fault region, and perform timing analysis on the detailed test data to determine a specific time point and a trigger condition of the fault occurrence; generate a fault diagnosis report of the storage chip and provide a corresponding repair suggestion according to the fault type, the fault region, the time point and the trigger condition of the fault occurrence.

[0012] In the storage chip engineering test system, the test data of the storage chip is obtained by: real-time collection of read-write operation data, temperature data and voltage data of the storage chip under different workloads by using a distributed sensor network; The distributed sensor network includes temperature sensors, voltage sensors and data transmission monitoring modules deployed at key nodes of the storage chip.

[0013] In a third aspect, the application further provides a computer readable storage medium, which comprises a storage chip engineering test method program, and the storage chip engineering test method program is executed by a processor to implement the steps of the storage chip engineering test method according to any one of the above aspects.

[0014] From the above, the embodiment of the application provides an engineering test method, system and medium of a storage chip, aiming to provide an efficient and accurate engineering test scheme of the storage chip, realizes accurate detection and diagnosis of chip faults through multi-dimensional data acquisition and intelligent analysis, and provides a reliable basis for chip production, maintenance and performance optimization. The specific technical scheme is as follows: distributed sensor networks are used to collect read-write operations, temperature and voltage data of the storage chip under different workloads in real time; a multi-dimensional feature extraction algorithm is used to extract statistical and correlation features through principal component analysis dimension reduction and sliding window segmentation processing; the feature data is input into a fault prediction model trained based on a deep learning algorithm, and whether the chip is faulty is judged in combination with a preset threshold; if there is a fault, the fault area is accurately located by using a dynamic probe test technology according to the fault type and the internal structure of the chip; then, time sequence analysis is performed on the detailed data of the fault area to determine the fault time point and the trigger condition, and finally, a fault diagnosis report is generated and repair suggestions are given by using a visual method and association rule mining technology. In addition, the application also provides a test system and a computer readable storage medium to realize the above method. The application has remarkable beneficial effects, the combination of multi-dimensional data acquisition and a deep learning model greatly improves the fault prediction accuracy and reduces the risk of misjudgment and missed judgment; the automatic process reduces manual intervention and optimizes the test efficiency; the fault trigger condition is analyzed in depth to realize comprehensive diagnosis; and good system compatibility facilitates integration with existing production detection equipment.

[0015] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent from the description, or can be learned by practice of the present application. The objects and other advantages of the present application will be realized and attained by the structure particularly pointed out in the written description and the appended drawings. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments of the present application. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation on the scope, and for those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0017] Figure 1 A high-level flowchart of an engineering test method of a storage chip provided by the embodiment of the present application is used to generate a diagnosis report containing specific repair suggestions.

[0018] Figure 2 A flowchart of an engineering test method of a storage chip provided by the embodiment of the present application; Figure 3 A flowchart of an engineering test method of a storage chip provided by the embodiment of the present application obtains multi-dimensional feature data; Figure 4 A flowchart of a training process of a fault prediction model of an engineering test method of a storage chip provided in an embodiment of the present application; Figure 5 A flowchart of judging whether a storage chip has a fault or not in an engineering test method of a storage chip provided in an embodiment of the present application. DETAILED DESCRIPTION

[0019] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. The components of the embodiments of the present application described and shown in the accompanying drawings can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0020] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. Meanwhile, in the description of the present application, the terms "first", "second", etc. are only used for differentiation in description, and cannot be understood as indicating or implying relative importance. It should be noted that the user information (including but not limited to user equipment information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in the present application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of related data need to comply with relevant laws, regulations and standards of relevant countries and regions.

[0021] Please refer to Figure 1 , Figure 1 is a high-level flowchart of an engineering test method of a storage chip in some embodiments of the present application. The flow starts from the "start" node, first collects test data (covering key parameters such as read-write, temperature, voltage, etc.), then extracts features from the data (using dimension reduction, segmentation, statistics, etc.), then inputs the processed features into the model for prediction, and the model outputs the fault type and probability, then enters the judgment link. If no fault is judged, the flow ends directly; if a fault is judged to exist, it enters the step-by-step scanning positioning link, locks the problem source through timing analysis (combined with time points and trigger conditions), and finally generates a diagnostic report containing specific repair suggestions, completing the whole process.

[0022] Please refer to Figure 2 ,Figure 2 is a flowchart of an engineering test method of a storage chip in some embodiments of the present application. The engineering test method of the storage chip is used in terminal equipment, such as computers, mobile terminals, etc. The engineering test method of the storage chip comprises the following steps: S201, obtaining test data of a storage chip, the test data comprising read-write operation data, temperature data and voltage data of the storage chip; S202, performing feature extraction on the test data based on a preset multi-dimensional feature extraction algorithm to obtain multi-dimensional feature data; S203, inputting the multi-dimensional feature data into a pre-trained fault prediction model, the fault prediction model being constructed based on a deep learning algorithm and trained by a large amount of historical test data and corresponding fault labels, and being used for predicting a fault type and a fault probability of the storage chip; S204, judging whether the storage chip has a fault according to the fault type and the fault probability output by the fault prediction model and in combination with a preset fault threshold; S205, if it is judged that there is a fault, then according to the fault type and internal structure information of the storage chip, a dynamic probe test technology is used to accurately locate a fault region of the storage chip; S206, obtaining detailed test data of the fault region and performing time sequence analysis on the detailed test data to determine a specific time point and a trigger condition of the fault occurrence; S207, generating a fault diagnosis report of the storage chip according to the fault type, the fault region, the fault occurrence time point and the trigger condition, and providing a corresponding repair suggestion.

[0023] Among them, through the distributed sensor network, temperature sensors, voltage sensors and data transmission monitoring modules are deployed at the key nodes of the storage chip to collect read-write operation data, temperature data and voltage data of the chip under different workloads in real time, providing multi-dimensional original information for subsequent analysis. Then, the test data is processed by using a multi-dimensional feature extraction algorithm, the principal component analysis algorithm is used to remove data redundancy, the sliding window technology is used to capture the data trend in segments, and the statistical features such as mean and variance and the correlation features between different types of data are extracted, so as to obtain effective feature data in multiple dimensions. Subsequently, the feature data is input into a fault prediction model constructed based on a deep learning algorithm, the model divides the training set, the verification set and the test set by using cross-validation through a large amount of historical test data and corresponding fault labels, and adjusts the number of layers, the number of neurons, the learning rate and other hyperparameters of the deep learning network to train, so as to accurately predict the fault type and the fault probability of the storage chip. Based on the output result of the model, according to the determination rule, the fault probability of the same fault type within a preset time is obtained, compared with a preset fault threshold and counted, and when the fault probability is greater than or equal to the preset threshold for three times in succession, it is determined that the storage chip has a fault, so as to reduce the misjudgment rate. If it is judged that there is a fault, then according to the fault type and the internal structure information of the storage chip, the dynamic probe test technology is used to perform regional-level scanning, gradually narrowing to block-level, page-level and the smallest storage unit block, the real-time electrical characteristic data obtained by comparing the probe scanning and the standard parameters in the address mapping table are used to identify the abnormal storage unit physical address, and the boundary scan technology is used to verify and locate the result, so as to realize accurate positioning of the fault area. Then, the detailed test data of the fault area is obtained, timing analysis is performed, and the specific time point and the triggering condition of the fault are determined. Finally, according to the fault type, the fault area, the fault time point and the triggering condition, visual means such as heat map, timing diagram and box plot are used to intuitively display the fault information, the association rule mining technology is used to automatically label the fault triggering condition, the cause-and-effect relationship chain of abnormal parameter combination and fault type is presented in the form of decision tree, a comprehensive fault diagnosis report is generated and corresponding repair suggestions are provided, and the systematic test and diagnosis of the storage chip are completed.

[0024] According to the embodiment of the application, the test data of the storage chip is obtained, including: The read-write operation data, temperature data and voltage data of the storage chip under different workloads are collected in real time by using the distributed sensor network. The distributed sensor network includes temperature sensors, voltage sensors and data transmission monitoring modules deployed at the key nodes of the storage chip.

[0025] The process of obtaining the storage chip test data relies on a distributed sensor network architecture. The network constructs a comprehensive data acquisition system by deploying temperature sensors, voltage sensors and data transmission monitoring modules at key nodes of the storage chip, such as power pins, data transmission channel interfaces, and heat concentration areas. During the operation of the chip, different workloads will cause the chip to produce diversified operating states. At this time, the temperature sensor can sense the temperature changes of each region of the chip in real time and capture the local overheating phenomenon caused by the increase of the load. The voltage sensor accurately monitors the power supply voltage and voltage fluctuation of each node of the chip, and discovers voltage abnormalities in time. The data transmission monitoring module is responsible for recording the read-write operation data of the chip, including data transmission frequency, read-write instruction response time and other information. These sensors and monitoring modules work together to collect read-write operation data, temperature data and voltage data of the storage chip under different workloads in a high-frequency and high-precision manner, providing comprehensive and reliable raw data basis for subsequent fault prediction, positioning and diagnosis, and ensuring that the test results can accurately reflect the actual operating state and potential fault hidden danger of the chip.

[0026] Please refer to Figure 3 , Figure 3 is a flowchart of obtaining multiple dimensional feature data of a storage chip engineering test method in some embodiments of the present application. According to the embodiment of the present application, the test data is subjected to feature extraction based on a preset multi-dimensional feature extraction algorithm to obtain multiple dimensional feature data, specifically: S301, using principal component analysis algorithm to reduce dimension of test data, removing data redundancy; S302, segmenting the test data by sliding window technology to capture the change trend of the data in different time windows; S303, extracting statistical features including mean, variance and other statistical quantities from the test data, and correlation features between different types of test data.

[0027] Among them, first, the principal component analysis (PCA) algorithm is used to reduce the dimension of the original test data. Because the temperature, voltage, read-write operation and other multi-source data collected by the distributed sensor network exist dimension redundancy (for example, temperature and voltage data may exist collinearity), PCA maps high-dimensional data to low-dimensional space through orthogonal transformation, retains the main variance information of the data, removes noise and redundant features, thereby effectively reducing the subsequent calculation complexity. Secondly, the sliding window technology is used to segment the reduced data. According to the working characteristics and failure occurrence law of the storage chip, a suitable time window width (such as 10ms-100ms) is set, and the window is slid on the time series to segment the data dynamically. The data in each window is regarded as an independent sample, and the trend of the data in the window (such as the rising / descending slope, periodic fluctuation) is analyzed to capture the timing characteristics of the chip running state, such as sudden voltage fluctuation or temperature sudden change. Finally, two types of key features are extracted from the segmented data: one is the statistical feature, which calculates the mean, variance, standard deviation, skewness and other statistical quantities of the data in each window to describe the distribution characteristics of the data; the second is the correlation feature, which analyzes the correlation between different types of test data (such as the correlation between temperature and voltage fluctuation, the correlation between read-write operation frequency and data transmission error rate). By constructing a feature matrix, multi-dimensional data is converted into a quantifiable feature vector, providing a structured input for the subsequent deep learning model, effectively improving the accuracy and model generalization ability of fault prediction. The feature extraction method realizes the transformation from raw data to high-order features through dimension reduction, time series analysis and correlation mining, which not only preserves the essential features of the data, but also compresses the data size, laying a technical foundation for accurate fault diagnosis of storage chips.

[0028] Please refer to Figure 4 , Figure 4 is a flow chart of a training process of a fault prediction model of a storage chip engineering test method in some embodiments of the present application. According to the embodiment of the present application, in the training process of the fault prediction model, it includes: S401, divide the large amount of historical test data into a training set, a validation set and a test set in a cross-validation manner; S402, adjust the hyperparameters of the deep learning algorithm to optimize the accuracy and generalization ability of the fault prediction model; S403, the hyperparameters at least include the number of layers, the number of neurons and the learning rate of the deep learning network.

[0029] The training process of the fault prediction model divides historical test data by hierarchical k-fold cross-validation, allocates the data set containing normal state and various fault types (such as bit flip, timing violation, temperature drift) to the training set, validation set and test set according to a preset ratio (such as 70:15:15), and ensures that the distribution ratio of fault types in each data set is consistent with the actual scene, for example, the training data of NAND Flash chips need to balance the sample size of different fault types such as programming interference and read interference. The combination of grid search and Bayesian optimization is used to systematically optimize the hyperparameters of the deep learning network, including: constructing a hybrid model that can capture temporal and spatial features, increasing the number of neurons in the feature fusion layer for fault types with strong temperature-voltage correlation; use the cosine annealing learning rate scheduling strategy to use a larger learning rate to quickly converge in the early stage of training, and gradually reduce the learning rate in the later stage to escape local optimal solution; set appropriate Dropout rate and L2 regularization coefficient to prevent overfitting. During the training process, the model performance indicators (precision, recall, F1 score) are evaluated in real time through the validation set, and the early stopping mechanism is enabled to prevent overfitting, and finally the generalization ability of the model is verified by blind test on the test set. Through data hierarchical processing, dynamic hyperparameter optimization and multi-index evaluation system, this method effectively improves the fault prediction accuracy and generalization ability of the model for storage chips of different process nodes and architecture.

[0030] Please refer to Figure 5 , Figure 5 is a flowchart of a method for determining whether a storage chip has a fault in some embodiments of the present application. According to the embodiments of the present application, the fault type and fault probability output by the fault prediction model are combined with a preset fault threshold to determine whether the storage chip has a fault, specifically: S501, obtaining the fault probability of the same fault type within a preset time; S502, comparing the fault probability with the preset fault threshold and performing counting processing; S503, if the fault probability is greater than or equal to the preset fault threshold for three consecutive times, it is determined that the storage chip has a fault, so as to reduce the false positive rate.

[0031] The failure judgment process of the storage chip is based on the output result of the failure prediction model, and a scientific statistical mechanism is combined to reduce the risk of misjudgment. Specifically, the system obtains the predicted failure probability of the same failure type within a preset time window (such as 10 minutes) in real time. The time window is set according to the typical failure incubation period of the storage chip and the test scene requirement. For the predicted failure probability each time, it is compared with a preset failure threshold (such as 0.7, which can be adjusted according to the chip reliability requirement and historical data statistical analysis), and the results meeting the condition are counted. When the failure probability of a failure type is greater than or equal to the preset threshold in three consecutive predictions, the system determines that the storage chip has a failure. This determination logic introduces the rule of "three consecutive trigger threshold", effectively filters the accidental false reports caused by data fluctuations and model prediction errors, significantly reduces the misjudgment rate compared with single threshold judgment, ensures the reliability of the failure diagnosis result, and provides accurate basis for subsequent failure positioning and repair.

[0032] According to the embodiment of the present application, the dynamic probe test technology is used to accurately position the failure area of the storage chip, specifically: The dynamic probe test technology is based on the preliminary failure range output by the failure prediction model, and first performs area-level scanning, and then gradually narrows down to block-level, page-level and finally the smallest storage unit block; By comparing the real-time electrical characteristic data obtained by the probe scanning with the standard parameters in the address mapping table, the physical address of the abnormal storage unit is identified; The boundary scan technology is used to verify the positioning result, and the boundary range of the failure unit is further confirmed by injecting test vectors into adjacent normal units.

[0033] Among them, the dynamic probe test technology realizes the accurate positioning of the fault area through hierarchical scanning and bidirectional verification mechanism. Based on the preliminary fault range (such as a certain bank or die) output by the fault prediction model, the test system first starts the regional scanning mode, uses the high-density probe array to detect the target area for coarse-grained electrical characteristics, and obtains the voltage and current distribution cloud diagram. Then, according to the regional scanning results, the detection range is gradually narrowed to the block level (Block), page level (Page), and finally focused on the minimum storage unit block (such as the physical page in NAND Flash or the row / column in DRAM). In the scanning process, the system compares the electrical characteristic data (such as threshold voltage, capacitance value) collected by the probe with the standard parameters of the address mapping table established in the chip design stage in real time, and identifies the physical address of the abnormal storage unit by constructing the deviation matrix. To ensure the reliability of the positioning results, the system further adopts boundary scan technology for secondary verification: injecting specific test vectors (such as checkerboard pattern, step code) into the normal storage units adjacent to the fault unit, monitoring the integrity and timing characteristics of the response signal, and verifying the boundary range of the fault unit according to the physical design rules, finally improving the positioning accuracy to the single storage unit level. Through the three-dimensional positioning strategy of prediction guidance - layer-by-layer fine scanning - boundary verification, this technology effectively solves the low efficiency problem caused by blind scanning in traditional probe test, realizes the rapid and accurate positioning of the fault area, and provides key support for subsequent chip repair and yield improvement.

[0034] According to the embodiment of the application, the fault diagnosis report of the storage chip is generated, comprising: The heat map is used to intuitively display the distribution density of the fault area in the physical layout of the chip, and the timing diagram is used to present the correlation between the fault occurrence time point and the system operation; The box plot is used to compare the statistical differences of key parameters such as voltage fluctuation range and temperature extreme value at the fault time and in the normal state; The association rule mining technology is used to automatically label the fault triggering condition, and the causal relationship chain between the abnormal parameter combination and the fault type is displayed in the form of decision tree in the report.

[0035] The generation process of the fault diagnosis report is deeply integrated with multi-dimensional visualization and data mining technology, and a comprehensive and traceable fault analysis system is constructed. First, the heat map is used to intuitively display the distribution density of the fault area in the physical layout of the chip, and the red, orange, yellow, green and blue gradient color scales are used to represent the fault probability, and the chip layout information is combined to accurately locate the high-incidence area of the fault (such as the vicinity of a specific Bank or I / O interface). At the same time, the time sequence diagram is used to associate and map the fault occurrence time point with the system operation (such as the erase-write cycle, the temperature sudden change moment), and the time sequence characteristics of the fault occurrence are clearly presented, such as whether it is related to a specific instruction sequence or a temperature fluctuation period. At the parameter analysis level, the system uses the box plot to compare the statistical differences of the key parameters (such as the voltage fluctuation range, the temperature extreme value) at the fault time and in the normal state, and quantifies the abnormal degree through the median, the interquartile range and other indicators. The most innovative is that the system uses the association rule mining technology (such as the Apriori algorithm) to automatically identify the fault triggering conditions, sets the minimum support and confidence thresholds (such as support ≥ 10%, confidence ≥ 80%), mines the causal relationship chain between the abnormal parameter combination (such as temperature > 85℃ and voltage < 2.9V) and the fault type (such as bit flip), and presents it in the form of a decision tree. Each branch node of the decision tree represents an abnormal parameter condition, and the leaf node corresponds to a specific fault type, which fully shows the conduction path from parameter abnormality to fault occurrence. The report generation mechanism not only realizes the visualization of the fault information, but also reveals the internal logic of the fault occurrence through the data mining technology, provides data-driven decision basis for chip design optimization (such as enhancing the heat dissipation of a specific area), test strategy adjustment (such as increasing the high-temperature and high-voltage stress test), and significantly improves the reliability engineering level of the storage chip.

[0036] According to the embodiment of the application, further comprising: A plurality of storage chip testing devices are networked, and each device uploads encrypted test data to a blockchain network, the test data including original test data and fault diagnosis results; A federated learning algorithm is used to collaboratively train a fault prediction model without sharing original data, and the model is deployed on edge nodes and a central server; Natural language processing and semantic analysis are performed on historical test data, fault diagnosis reports and repair records, and a knowledge graph continuously updated by a graph neural network is constructed; According to the model of the chip to be tested, the historical fault record and the real-time test data, individualized test parameter configuration is generated from the knowledge graph, including probe scanning frequency and fault threshold.

[0037] To further improve the synergy and intelligent level of storage chip testing, a distributed testing system based on blockchain and federated learning is constructed. First, by networking multiple storage chip testing devices, a distributed testing network is formed, and each device uploads the encrypted original test data (such as read-write operation data, temperature data, and voltage data) and fault diagnosis results to the blockchain network. Using the decentralized and tamper-proof features of blockchain, the security and credibility of the test data are ensured, and distributed storage and sharing of data are realized. On this basis, federated learning algorithm is used for cross-device collaborative training. Without sharing the original data, each testing device trains a fault prediction model based on local data, and only uploads the encrypted model parameter gradient to the central server. The server updates the global model by aggregating the gradient, and distributes the updated model to each device. This mode not only protects data privacy, but also realizes the fusion and utilization of multi-source data, improves the generalization ability of the fault prediction model, and enables the model to adapt to the testing needs of different production batches and different types of storage chips. The model is deployed on the edge node and the central server, supporting real-time online prediction. In addition, the system processes and analyzes historical test data, fault diagnosis reports, and repair records through natural language processing and semantic analysis, and constructs a dynamic knowledge graph. Using graph neural network technology, the system continuously mines the association relationships between entities such as fault types, trigger conditions, repair strategies, and chip models, and updates the knowledge graph in real time. When testing a new storage chip, the system can quickly retrieve similar cases and association rules from the knowledge graph based on the model, historical fault records, and real-time test data of the chip to be tested, and automatically generate personalized test parameter configurations, including probe scanning frequency (such as increasing the scanning frequency for high-temperature sensitive chips), fault threshold (dynamically adjusting according to chip process characteristics), etc., to realize adaptive optimization of testing strategies and significantly improve testing efficiency and accuracy, providing intelligent decision support for storage chip quality control throughout the life cycle.

[0038] According to the embodiment of the present application, the step of federated learning collaborative training comprises: Each testing device trains a fault prediction model based on local data to generate model parameter gradient; The model parameter gradient is encrypted and uploaded to the central server, and the server aggregates the gradient to update the global model; The central server distributes the updated model to each testing device, and each device continues to train based on the new model; Differential privacy technology is used to protect the privacy of local training data.

[0039] In the federated learning collaborative training mechanism, cross-device model optimization is realized through multiple rounds of iteration and privacy protection technology: each test device independently trains a fault prediction model based on locally stored test data (such as temperature-voltage fluctuation data of a batch of NAND flash chips), calculates the model parameter gradient using an optimization algorithm such as stochastic gradient descent (SGD), and then encrypts the gradient using homomorphic encryption or secure multi-party computation (MPC) technology (such as using the Paillier homomorphic encryption algorithm to encrypt the gradient and upload it to the central server; the central server collects the encrypted gradients of all devices, calculates the average gradient value through a secure aggregation protocol, decrypts the global gradient update value after decryption, and updates the global model parameters; the updated global model parameters are distributed to each device, and each device continues local training based on the new parameters to form a closed-loop iterative process; to further enhance privacy protection, each device adds noise to the gradient before uploading using the Laplace mechanism, balancing model accuracy and privacy protection strength. This mechanism realizes cross-device knowledge sharing without sharing raw data, enabling the fault prediction model to learn more extensive fault patterns (such as temperature sensitivity differences of chips with different process nodes). It provides a safe and feasible technical solution for cross-enterprise and cross-factory collaborative testing in the semiconductor industry.

[0040] The application further discloses an engineering test system for a storage chip, comprising a memory and a processor, wherein the memory comprises an engineering test method program for a storage chip, and the engineering test method program for a storage chip is executed by the processor to realize the following steps: Obtaining test data of the storage chip, wherein the test data comprises read-write operation data, temperature data and voltage data of the storage chip; Performing feature extraction on the test data based on a preset multi-dimensional feature extraction algorithm to obtain feature data in multiple dimensions; Inputting the feature data in multiple dimensions into a pre-trained fault prediction model, wherein the fault prediction model is constructed based on a deep learning algorithm, and is trained by a large amount of historical test data and corresponding fault labels, and is used for predicting a fault type and a fault probability of the storage chip; Judging whether the storage chip has a fault according to the fault type and the fault probability output by the fault prediction model and in combination with a preset fault threshold; If it is judged that there is a fault, performing accurate positioning on a fault region of the storage chip by using a dynamic probe test technology according to the fault type and internal structure information of the storage chip; Obtaining detailed test data of the fault region, and performing timing analysis on the detailed test data to determine a specific time point and a trigger condition of the fault; According to the fault type, fault area, fault occurrence time point and trigger condition, a fault diagnosis report of the storage chip is generated, and a corresponding repair suggestion is provided.

[0041] Among them, through the distributed sensor network, temperature sensors, voltage sensors and data transmission monitoring modules are deployed at the key nodes of the storage chip, real-time collection of read-write operation data, temperature data and voltage data of the chip under different workloads is performed, and multi-dimensional original information is provided for subsequent analysis. Then, the test data is processed by using a multi-dimensional feature extraction algorithm, the principal component analysis algorithm is used to remove data redundancy, the sliding window technology is used to capture the data trend in segments, and the statistical features such as mean and variance and the correlation features between different types of data are extracted, so as to obtain effective feature data in multiple dimensions. Subsequently, the feature data is input into a fault prediction model constructed based on a deep learning algorithm, the model divides the training set, the verification set and the test set by using cross-validation through a large amount of historical test data and corresponding fault labels, and adjusts the number of layers, the number of neurons, the learning rate and other hyperparameters of the deep learning network for training, so as to accurately predict the fault type and the fault probability of the storage chip. Based on the output result of the model, according to the determination rule, the fault probability of the same fault type within a preset time is obtained, compared with a preset fault threshold and counted, and when the fault probability is greater than or equal to the preset threshold for three times in succession, it is determined that the storage chip has a fault, so as to reduce the misjudgment rate. If it is judged that there is a fault, then according to the fault type and the internal structure information of the storage chip, the dynamic probe test technology is used to perform regional-level scanning, gradually narrowing to block-level, page-level and the smallest storage unit block, the real-time electrical characteristic data obtained by comparing the probe scanning and the standard parameters in the address mapping table are used to identify the abnormal storage unit physical address, and the boundary scan technology is used to verify and locate the result, so as to realize accurate positioning of the fault area. Then, the detailed test data of the fault area is obtained, timing analysis is performed, the specific time point and the trigger condition of the fault occurrence are determined. Finally, according to the fault type, the fault area, the fault occurrence time point and the trigger condition, the fault information is intuitively displayed by using visualization means such as heat map, timing diagram and box plot, the fault trigger condition is automatically labeled by using the association rule mining technology, the causal relationship chain of the abnormal parameter combination and the fault type is presented in the form of a decision tree, a comprehensive fault diagnosis report is generated and a corresponding repair suggestion is provided, and the systematic test and diagnosis of the storage chip are completed.

[0042] According to the embodiment of the present application, the test data of the storage chip is obtained, including: The read-write operation data, temperature data and voltage data of the storage chip under different workloads are collected in real time by using the distributed sensor network. The distributed sensor network includes temperature sensors, voltage sensors and data transmission monitoring modules deployed at the key nodes of the storage chip.

[0043] The process of obtaining the storage chip test data relies on a distributed sensor network architecture. The network constructs a comprehensive data acquisition system by deploying temperature sensors, voltage sensors and data transmission monitoring modules at key nodes of the storage chip, such as power pins, data transmission channel interfaces, and heat concentration areas. During the operation of the chip, different workloads will cause the chip to produce diversified operating states. At this time, the temperature sensor can sense the temperature changes of each region of the chip in real time and capture the local overheating phenomenon caused by the increase of the load. The voltage sensor accurately monitors the power supply voltage and voltage fluctuation of each node of the chip, and discovers voltage abnormalities in time. The data transmission monitoring module is responsible for recording the chip read-write operation data, including data transmission frequency, read-write instruction response time and other information. These sensors and monitoring modules work together to collect read-write operation data, temperature data and voltage data of the storage chip under different workloads in a high-frequency and high-precision manner, providing a comprehensive and reliable raw data basis for subsequent fault prediction, positioning and diagnosis, and ensuring that the test results can accurately reflect the actual operating state and potential fault hidden danger of the chip.

[0044] According to the embodiment of the application, the test data is subjected to feature extraction based on a preset multi-dimensional feature extraction algorithm to obtain feature data of multiple dimensions, specifically: The principal component analysis algorithm is used to reduce the dimension of the test data and remove data redundancy; The test data is subjected to segmented processing through the sliding window technology to capture the change trend of the data in different time windows; Statistical features including mean, variance and other statistical quantities, and correlation features between different types of test data are extracted from the test data.

[0045] Among them, first, the principal component analysis (PCA) algorithm is used to reduce the dimension of the original test data. Since the temperature, voltage, read-write operation and other multi-source data collected by the distributed sensor network have dimension redundancy (for example, temperature and voltage data may have collinearity), PCA maps high-dimensional data to low-dimensional space through orthogonal transformation, retains the main variance information of the data, removes noise and redundant features, thereby effectively reducing the subsequent calculation complexity. Secondly, the sliding window technology is used to segment the data after dimension reduction. According to the working characteristics and failure occurrence law of the storage chip, a suitable time window width (such as 10ms-100ms) is set, and the sliding window is slid on the time sequence to segment the data dynamically. The data in each window is regarded as an independent sample, and the change trend (such as the rising / descending slope, periodic fluctuation) of the data in the window is analyzed to capture the timing characteristics of the chip running state, such as sudden voltage fluctuation or temperature sudden change. Finally, two types of key features are extracted from the segmented data: one is the statistical feature, which calculates the mean, variance, standard deviation, skewness and other statistical quantities of the data in each window to describe the distribution characteristics of the data; The second is the correlation feature, which analyzes the correlation between different types of test data (such as the correlation between temperature and voltage fluctuation, the correlation between read-write operation frequency and data transmission error rate). By constructing a feature matrix, multi-dimensional data is converted into a quantifiable feature vector, providing a structured input for the subsequent deep learning model, effectively improving the accuracy and model generalization ability of fault prediction. The feature extraction method realizes the transformation from raw data to high-order features through dimension reduction, time series analysis and correlation mining, which not only retains the essential features of the data, but also compresses the data size, laying a technical foundation for accurate fault diagnosis of storage chips.

[0046] According to the embodiment of the application, the training process of the fault prediction model comprises: The large amount of historical test data is divided into a training set, a validation set and a test set by cross-validation; The accuracy and generalization ability of the fault prediction model are optimized by adjusting the hyperparameters of the deep learning algorithm; The hyperparameters at least include the number of layers, the number of neurons and the learning rate of the deep learning network.

[0047] The training process of the fault prediction model divides historical test data by hierarchical k-fold cross-validation, allocates the data set containing normal state and various fault types (such as bit flip, timing violation, temperature drift) to the training set, validation set and test set according to a preset proportion (such as 70:15:15), and ensures that the distribution proportion of fault types in each data set is consistent with the actual scene, for example, the training data of the NAND Flash chip needs to balance the sample size of different fault types such as programming interference and read interference. The combination of grid search and Bayesian optimization is used to systematically optimize the hyperparameters of the deep learning network, including: constructing a hybrid model that can capture temporal and spatial features, increasing the number of neurons in the feature fusion layer for fault types with strong temperature-voltage correlation; using the cosine annealing learning rate scheduling strategy, using a high learning rate to quickly converge in the early stage of training, and gradually reducing the learning rate in the later stage to escape local optimal solution; setting appropriate Dropout rate and L2 regularization coefficient to prevent overfitting. During the training process, the performance indicators (precision, recall, F1 score) of the model are evaluated in real time through the validation set, and the early stopping mechanism is enabled to prevent overfitting, and finally the generalization ability of the model is verified by blind test on the test set. Through data hierarchical processing, dynamic hyperparameter optimization and multi-index evaluation system, this method effectively improves the fault prediction accuracy and generalization ability of the model for storage chips of different process nodes and architecture.

[0048] According to the embodiment of the application, the fault type and the fault probability output according to the fault prediction model are combined with a preset fault threshold to determine whether the storage chip has a fault, specifically: Obtaining the fault probability of the same fault type within a preset time; Comparing the fault probability with the preset fault threshold and performing counting processing; If the fault probability is greater than or equal to the preset fault threshold for three consecutive times, it is determined that the storage chip has a fault, so as to reduce the misjudgment rate.

[0049] The failure judgment process of the storage chip is based on the output result of the failure prediction model, and a scientific statistical mechanism is combined to reduce the risk of misjudgment. Specifically, the system obtains the predicted failure probability of the same failure type within a preset time window (such as 10 minutes) in real time. The time window is set according to the typical failure incubation period of the storage chip and the test scene requirement. For the predicted failure probability each time, it is compared with a preset failure threshold (such as 0.7, which can be adjusted according to the chip reliability requirement and historical data statistical analysis), and the results meeting the condition are counted. When the failure probability of a failure type is greater than or equal to the preset threshold in three consecutive predictions, the system determines that the storage chip has a failure. This determination logic introduces the rule of “three consecutive trigger threshold”, effectively filters the accidental false reports caused by data fluctuations and model prediction errors, significantly reduces the misjudgment rate compared with single threshold judgment, ensures the reliability of the failure diagnosis result, and provides accurate basis for subsequent failure positioning and repair.

[0050] According to the embodiment of the present application, the dynamic probe test technology is used to accurately position the failure area of the storage chip, specifically: The dynamic probe test technology is based on the preliminary failure range output by the failure prediction model, and first performs area-level scanning, and then gradually narrows down to block-level, page-level and finally the smallest storage unit block; By comparing the real-time electrical characteristic data obtained by the probe scanning with the standard parameters in the address mapping table, the physical address of the abnormal storage unit is identified; The boundary scan technology is used to verify the positioning result, and the boundary range of the failure unit is further confirmed by injecting test vectors into adjacent normal units.

[0051] Among them, the dynamic probe test technology realizes the accurate positioning of the fault area through hierarchical scanning and bidirectional verification mechanism. Based on the preliminary fault range (such as a certain bank or die) output by the fault prediction model, the test system first starts the regional scanning mode, uses the high-density probe array to detect the target area for coarse-grained electrical characteristics, and obtains the voltage and current distribution cloud diagram. Then, according to the regional scanning results, the detection range is gradually narrowed to the block level (Block), page level (Page), and finally focused on the minimum storage unit block (such as the physical page in NAND Flash or the row / column in DRAM). In the scanning process, the system compares the electrical characteristic data (such as threshold voltage, capacitance value) collected by the probe with the standard parameters of the address mapping table established in the chip design stage in real time, and identifies the physical address of the abnormal storage unit by constructing the deviation matrix. To ensure the reliability of the positioning results, the system further adopts boundary scan technology for secondary verification: injecting specific test vectors (such as checkerboard pattern, step code) into the normal storage units adjacent to the fault unit, monitoring the integrity and timing characteristics of the response signal, and verifying the boundary range of the fault unit according to the physical design rules, finally improving the positioning accuracy to the single storage unit level. Through the three-dimensional positioning strategy of prediction guidance - layer-by-layer fine scanning - boundary verification, this technology effectively solves the low efficiency problem caused by blind scanning in traditional probe test, realizes the rapid and accurate positioning of the fault area, and provides key support for subsequent chip repair and yield improvement.

[0052] According to the embodiment of the present application, the fault diagnosis report of the storage chip is generated, comprising: Adopting a heat map to intuitively display the distribution density of the fault area in the physical layout of the chip, and presenting the correlation between the fault occurrence time point and the system operation through a timing diagram; Comparing the statistical differences of key parameters such as voltage fluctuation range and temperature extreme value at the fault time and in the normal state through a box plot; Using association rule mining technology to automatically label the fault trigger condition, and displaying the causal relationship chain between abnormal parameter combination and fault type in the form of decision tree in the report.

[0053] The generation process of the fault diagnosis report is deeply integrated with multi-dimensional visualization and data mining technology, and a comprehensive and traceable fault analysis system is constructed. First, the heat map is used to intuitively display the distribution density of the fault area in the physical layout of the chip, and the red, orange, yellow, green and blue gradient color scales are used to represent the fault probability, and the chip layout information is combined to accurately locate the high-incidence area of the fault (such as the vicinity of a specific Bank or I / O interface). At the same time, the time sequence diagram is used to associate and map the fault occurrence time point with the system operation (such as the erase-write cycle, the temperature sudden change moment), and the time sequence characteristics of the fault occurrence are clearly presented, such as whether it is related to a specific instruction sequence or a temperature fluctuation period. At the parameter analysis level, the system uses the box plot to compare the statistical differences of the key parameters (such as the voltage fluctuation range, the temperature extreme value) at the fault time and in the normal state, and quantifies the abnormal degree through the median, the interquartile range and other indicators. The most innovative is that the system uses the association rule mining technology (such as the Apriori algorithm) to automatically identify the fault triggering conditions, sets the minimum support and confidence thresholds (such as support ≥ 10%, confidence ≥ 80%), mines the causal relationship chain between the abnormal parameter combination (such as temperature > 85℃ and voltage < 2.9V) and the fault type (such as bit flip), and presents it in the form of a decision tree. Each branch node of the decision tree represents an abnormal parameter condition, and the leaf node corresponds to a specific fault type, which completely shows the conduction path from parameter abnormality to fault occurrence. This report generation mechanism not only realizes the visualization of fault information, but also reveals the internal logic of fault occurrence through data mining technology, provides data-driven decision basis for chip design optimization (such as enhancing the heat dissipation of a specific area), test strategy adjustment (such as increasing high-temperature and high-voltage stress test), and significantly improves the reliability engineering level of the storage chip.

[0054] According to the embodiment of the application, further comprising: A plurality of storage chip testing devices are networked, and each device uploads encrypted test data to a blockchain network, the test data including original test data and fault diagnosis results; A federated learning algorithm is used to collaboratively train a fault prediction model without sharing original data, and the model is deployed on edge nodes and a central server; Historical test data, fault diagnosis reports and repair records are subjected to natural language processing and semantic analysis, and a knowledge graph continuously updated by a graph neural network is constructed; According to the model of the chip to be tested, historical fault records and real-time test data, personalized test parameter configurations are generated from the knowledge graph, including probe scanning frequency and fault threshold.

[0055] To further improve the synergy and intelligent level of storage chip testing, a distributed testing system based on blockchain and federated learning is constructed. First, by networking multiple storage chip testing devices, a distributed testing network is formed, and each device uploads the encrypted original test data (such as read-write operation data, temperature data, and voltage data) and fault diagnosis results to the blockchain network. Using the decentralized and tamper-proof features of blockchain, the security and credibility of the test data are ensured, and distributed storage and sharing of data are realized. On this basis, federated learning algorithm is used for cross-device collaborative training. Without sharing the original data, each testing device trains a fault prediction model based on local data, and only uploads the encrypted model parameter gradient to the central server. The server updates the global model by aggregating the gradient, and distributes the updated model to each device. This mode not only protects data privacy, but also realizes the fusion and utilization of multi-source data, improves the generalization ability of the fault prediction model, and enables the model to adapt to the testing needs of different production batches and different types of storage chips. The model is deployed on the edge node and the central server, supporting real-time online prediction. In addition, the system processes and analyzes historical test data, fault diagnosis reports, and repair records through natural language processing and semantic analysis, and constructs a dynamic knowledge graph. Using graph neural network technology, the system continuously mines the association relationships between entities such as fault types, trigger conditions, repair strategies, and chip models, and updates the knowledge graph in real time. When testing a new storage chip, the system can quickly retrieve similar cases and association rules from the knowledge graph based on the model, historical fault records, and real-time test data of the chip to be tested, and automatically generate personalized test parameter configurations, including probe scanning frequency (such as increasing the scanning frequency for high-temperature sensitive chips), fault threshold (dynamically adjusting according to chip process characteristics), etc., to realize adaptive optimization of testing strategies and significantly improve testing efficiency and accuracy, providing intelligent decision support for storage chip quality control throughout the life cycle.

[0056] According to the embodiment of the present application, the step of federated learning collaborative training comprises: Each testing device trains a fault prediction model based on local data to generate model parameter gradient; The model parameter gradient is encrypted and uploaded to the central server, and the server aggregates the gradient to update the global model; The central server distributes the updated model to each testing device, and each device continues to train based on the new model; Differential privacy technology is used to protect the privacy of local training data.

[0057] In the mechanism, the federated learning collaborative training mechanism realizes cross-device model optimization through multiple rounds of iterations and privacy protection technologies: each test device independently trains a fault prediction model based on locally stored test data (such as temperature-voltage fluctuation data of a batch of NAND flash chips), calculates the model parameter gradient using an optimization algorithm such as stochastic gradient descent (SGD), and then encrypts the gradient using homomorphic encryption or secure multi-party computation (MPC) technology (such as using the Paillier homomorphic encryption algorithm to encrypt the gradient and upload it to the central server; the central server collects the encrypted gradients of all devices, calculates the average gradient value through a secure aggregation protocol, decrypts the global gradient update value after obtaining the global model parameters, and updates the global model parameters; the updated global model parameters are distributed to each device, and each device continues local training based on the new parameters to form a closed-loop iterative process; to further enhance privacy protection, each device adds noise to the gradient before uploading the gradient using the Laplace mechanism, balancing model accuracy and privacy protection strength. This mechanism realizes cross-device knowledge sharing without sharing raw data through gradient encryption transmission, differential privacy disturbance, and a secure aggregation protocol, enabling the fault prediction model to learn more extensive fault patterns (such as temperature sensitivity differences of chips with different process nodes). It provides a safe and feasible technical solution for cross-enterprise and cross-factory collaborative testing in the semiconductor industry.

[0058] The third aspect of the present application provides a computer readable storage medium, wherein the computer readable storage medium comprises a storage chip engineering test method program, and the storage chip engineering test method program is executed by a processor to realize the steps of the storage chip engineering test method according to any one of the preceding aspects.

[0059] The application discloses an engineering test method, system and medium for a storage chip, which realizes accurate diagnosis of chip faults through multi-dimensional data acquisition, intelligent analysis and cross-device cooperation mechanism. First, a distributed sensor network is adopted, temperature sensors, voltage sensors and data transmission monitoring modules are deployed at key nodes of the chip, read-write operation data, temperature data and voltage data under different workloads are collected in real time, and original information is provided for subsequent analysis; then, a multi-dimensional feature extraction algorithm is used to extract statistical features and correlation features through principal component analysis dimension reduction and sliding window segmentation processing, and a structured feature vector is formed; subsequently, the feature data is input into a deep learning fault prediction model, the model divides the training set, the validation set and the test set through cross-validation, and optimizes hyperparameters such as the number of network layers and the number of neurons, and realizes fault type and probability prediction; based on the determination rule, when the probability of the same fault type exceeds the preset threshold for three times in succession, it is determined that there is a fault; if there is a fault, the dynamic probe test technology is used, first, the regional level scanning is performed, and then the minimum storage unit block is gradually narrowed, the fault address is identified by comparing the electrical characteristic data with the standard parameters, and the boundary scan technology is verified; then, the detailed data of the fault region is acquired for timing analysis to determine the fault time point and the trigger condition; finally, the heat map, timing chart and other visualization means are used, and the fault diagnosis report is generated and repair suggestions are provided in combination with the association rule mining technology. In addition, through the distributed test system extended in the claims, the application uploads encrypted data to the blockchain after networking multiple devices, cooperatively trains the model under the premise of protecting privacy by using federated learning, generates personalized test parameters by constructing a knowledge graph, realizes adaptive optimization of the test strategy, and ensures the consistency and advancement of the whole process technical scheme.

[0060] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only illustrative, for example, the division of the units is only a logical function division, and actual implementation can have another division mode, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the displayed or discussed components can be through some interface, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0061] The units described above as separate components can or can not be physically separated, and the components shown as units can or can not be physical units; they can be located in one place or distributed on multiple network units; part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment scheme.

[0062] In addition, each function unit in each embodiment of the present application can be integrated in one processing unit, or each unit can be separately taken as one unit, or two or more units can be integrated in one unit; the integrated unit can be realized in the form of hardware or in the form of hardware plus software function unit.

[0063] Those skilled in the art can understand that all or part of the steps of the above-mentioned method embodiments can be completed by relevant hardware instructed by programs, and the foregoing programs can be stored in a readable storage medium, and when the programs are executed, the steps of the above-mentioned method embodiments are executed; and the foregoing storage medium includes various storage media that can store program codes, such as mobile storage devices, read-only memories, random access memories, magnetic discs or optical discs.

[0064] Alternatively, when the integrated unit of the present application is realized in the form of a software function module and sold or used as an independent product, it can also be stored in a readable storage medium. Based on such understanding, the technical solutions of the embodiments of the present application can be embodied in the form of a software product in essence or the part that contributes to the prior art, and the software product is stored in a storage medium, including a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in the embodiments of the present application. The foregoing storage medium includes various storage media that can store program codes, such as mobile storage devices, ROMs, RAMs, magnetic discs or optical discs.

Claims

1. A method of engineering testing a memory chip, the method comprising: The method comprises the following steps: acquiring test data of a storage chip, the test data comprising read-write operation data, temperature data and voltage data of the storage chip; performing feature extraction on the test data based on a preset multi-dimensional feature extraction algorithm to obtain feature data of multiple dimensions; inputting the feature data of multiple dimensions into a pre-trained fault prediction model, the fault prediction model being constructed based on a deep learning algorithm and trained by a large amount of historical test data and corresponding fault labels, and being used for predicting a fault type and a fault probability of the storage chip; judging whether the storage chip has a fault based on the fault type and the fault probability output by the fault prediction model and in combination with a preset fault threshold; if it is judged that there is a fault, performing accurate positioning of a fault region of the storage chip by using a dynamic probe test technology according to the fault type and internal structure information of the storage chip; acquiring detailed test data of the fault region and performing time sequence analysis on the detailed test data to determine a specific time point and a trigger condition of fault occurrence; generating a fault diagnosis report of the storage chip and providing a corresponding repair suggestion according to the fault type, the fault region, the time point of fault occurrence and the trigger condition.

2. The method of claim 1, wherein, The acquisition of the test data of the storage chip comprises: collecting read-write operation data, temperature data and voltage data of the storage chip under different workloads in real time by using a distributed sensor network; the distributed sensor network comprises temperature sensors, voltage sensors and data transmission monitoring modules arranged at key nodes of the storage chip.

3. The method of claim 1, wherein the method further comprises: The feature extraction on the test data based on the preset multi-dimensional feature extraction algorithm to obtain feature data of multiple dimensions comprises: performing dimension reduction processing on the test data by using a principal component analysis algorithm to remove data redundancy; performing segmentation processing on the test data by using a sliding window technology to capture the change trend of the data in different time windows; extracting statistical features including mean, variance and the like from the test data, and correlation features between different types of test data.

4. The method of claim 1, wherein the method further comprises: In the training process of the fault prediction model, the following steps are included: dividing the large amount of historical test data into a training set, a validation set and a test set by using a cross-validation method; optimizing the accuracy and generalization ability of the fault prediction model by adjusting hyperparameters of the deep learning algorithm; the hyperparameters at least include the number of layers, the number of neurons and the learning rate of the deep learning network.

5. The method of claim 1, wherein the method further comprises: The judgment of whether the storage chip has a fault based on the fault type and the fault probability output by the fault prediction model and in combination with a preset fault threshold comprises: acquiring fault probabilities of the same fault type within a preset time; comparing the fault probabilities with the preset fault threshold and performing counting processing; if the fault probability is greater than or equal to the preset fault threshold for three consecutive times, it is determined that the storage chip has a fault, so as to reduce the misjudgment rate.

6. The method of claim 1, wherein The accurate positioning of the fault region of the storage chip by using the dynamic probe test technology comprises: the dynamic probe test technology first performs region-level scanning based on the preliminary fault range output by the fault prediction model, and then gradually narrows down to block-level, page-level and finally the smallest storage unit block. By comparing the real-time electrical characteristic data obtained by probe scanning with the standard parameters in the address mapping table, the physical address of the abnormal storage unit is identified; The boundary scan technology is used to verify the positioning result, and the boundary range of the faulty unit is further confirmed by injecting test vectors into adjacent normal units.

7. The method of claim 1, wherein the method further comprises: The fault diagnosis report of the storage chip is generated, including: The heat map is used to intuitively display the distribution density of the fault area in the physical layout of the chip, and the timing chart is used to present the correlation between the fault occurrence time point and the system operation; The statistical differences of key parameters such as voltage fluctuation range and temperature extreme value between fault time and normal state are compared through the box plot; The association rule mining technology is used to automatically label the fault trigger condition, and the causal relationship chain between abnormal parameter combination and fault type is displayed in the form of decision tree in the report.

8. An engineering test system for memory chips, characterized by A memory and a processor are included, the memory includes a storage chip engineering test method program, and the storage chip engineering test method program is executed by the processor to realize the following steps: Obtain test data of the storage chip, the test data including read-write operation data, temperature data and voltage data of the storage chip; Based on a preset multi-dimensional feature extraction algorithm, feature extraction is performed on the test data to obtain multi-dimensional feature data; The multi-dimensional feature data is input into a pre-trained fault prediction model, the fault prediction model is constructed based on a deep learning algorithm, and is trained through a large amount of historical test data and corresponding fault labels, and is used to predict the fault type and fault probability of the storage chip; According to the fault type and fault probability output by the fault prediction model, and in combination with a preset fault threshold, it is judged whether the storage chip has a fault; If it is judged that there is a fault, according to the fault type and internal structure information of the storage chip, a dynamic probe test technology is used to accurately locate the fault area of the storage chip; Obtain detailed test data of the fault area, and perform timing analysis on the detailed test data to determine the specific time point and trigger condition of the fault occurrence; According to the fault type, fault area, fault occurrence time point and trigger condition, a fault diagnosis report of the storage chip is generated, and corresponding repair suggestions are provided.

9. The system for engineering testing of memory chips according to claim 8, wherein, The test data of the storage chip is obtained, including: The distributed sensor network is used to collect read-write operation data, temperature data and voltage data of the storage chip under different workloads in real time; The distributed sensor network includes temperature sensors, voltage sensors and data transmission monitoring modules deployed at key nodes of the storage chip.

10. A computer-readable storage medium, characterized in that, The computer readable storage medium includes a storage chip engineering test method program, and the storage chip engineering test method program is executed by the processor to realize the steps of the storage chip engineering test method in any one of claims 1 to 7.

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