Controller, method and equipment for verifying storage data and storage medium

Abstract

The invention provides a controller, method and device for verifying stored data and a storage medium. The controller obtains a data writing instruction and a verification writing instruction; in response to the data writing instruction, writing the to-be-written data block into the first memory; in response to the write verification instruction, obtaining a to-be-read data block based on the read address; calculating a read address and a to-be-read data block to obtain a write check code; the to-be-read data block is a part of the to-be-written data block; obtaining a read verification instruction; in response to the read verification instruction, obtaining a read data block from the first memory based on the read address; calculating a read address and a read data block to obtain a read check code; and comparing the write check code with the read check code to obtain a comparison result. According to the technical scheme, whether the read data block is abnormal or not can be checked by calculating the read data block and the read address corresponding to the read data block, and therefore safe operation and performance of the ADAS chip are guaranteed.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a controller, method, device and storage medium for verifying stored data. Background Technology

[0002] ADAS (Advanced Driver Assistance Systems) chips include a memory. Within the ADAS chip, the memory stores and processes sensor data, image data, algorithm data, etc., to support various functions and algorithms of the ADAS system.

[0003] To protect the data in memory and ensure the normal operation of ADAS chips, error correction codes (ECC) or cyclic redundancy checks (CRC) algorithms are often used in related technologies to verify the stored data.

[0004] However, ECC occupies a large storage area and bandwidth, while the CRC algorithm fails when the data block to be written and the data block to be read are inconsistent, thus affecting the safe operation and performance of the ADAS chip and reducing the user experience. Summary of the Invention

[0005] This application provides a controller, method, device, and storage medium for verifying stored data. When the data block to be written and the data block to be read are inconsistent, the method calculates the read address corresponding to the read data block to verify whether the read data block is abnormal, ensuring the safe operation and performance of the ADAS chip and thus improving the user experience. The technical solution is as follows:

[0006] According to a first aspect of the embodiments of this application, a controller for verifying stored data is provided, comprising:

[0007] The configuration module is used to obtain write data instructions and write verification instructions; the write verification instructions include a read address.

[0008] A write control module is used to write the data block to be written into the first memory in response to the write data command;

[0009] A write verification module is used to respond to the write verification instruction by obtaining a data block to be read based on the read address; calculating the read address and the data block to be read to obtain a write verification code; the data block to be read is a part of the data block to be written.

[0010] The configuration module is further configured to obtain a read verification instruction; the read verification instruction includes the read address;

[0011] A read verification module is configured to, in response to the read verification instruction, retrieve the read data block from the first memory based on the read address; calculate the read address and the read data block to obtain a read verification code; compare the write verification code and the read verification code to obtain a comparison result; and the comparison result indicates whether the read data block is abnormal.

[0012] In some embodiments, a write data stream is generated during the process of the write control module writing the data block to be written into the first memory;

[0013] The write verification module obtains the data block to be read based on the read address, including:

[0014] The write verification module obtains the data block to be read from the write data stream based on the read address.

[0015] In some embodiments, the read address includes an initial read address and an end read address; the initial read address and the end read address indicate a first memory address range corresponding to the data block to be read; the data block to be read includes at least one piece of data to be read, and the data to be read corresponds one-to-one with the first memory address.

[0016] The step of calculating the read address and the data block to be read to obtain the write verification code includes:

[0017] Perform an XOR operation on the (i+1)th piece of data to be read and the first memory address corresponding to the (i+1)th piece of data to be read to obtain the (i+1)th first XOR value; i is an integer greater than or equal to 1;

[0018] Add the (i+1)th first XOR value and the ith first intermediate check code to obtain the (i+1)th first intermediate check code;

[0019] The write check code is obtained by calculating the (i+1)th first intermediate check code.

[0020] In some embodiments, the controller further includes a read control module;

[0021] The configuration module is further configured to acquire a read data instruction; the read data instruction includes the read address;

[0022] The read control module is configured to read the read data block from the first memory based on the read address in response to the read data instruction; wherein a read data stream is generated during the process of the read control module reading the data block to be read.

[0023] The read verification module is used to respond to the read verification instruction and obtain the read data block from the read data stream based on the read address.

[0024] In some embodiments, the read data block includes at least one read data; the read data corresponds one-to-one with the first memory address;

[0025] The calculation of the read address and the read data block to obtain the read check code includes:

[0026] Perform an XOR operation on the (i+1)th read data and the first memory address corresponding to the (i+1)th read data to obtain the (i+1)th second XOR value;

[0027] Add the (i+1)th second XOR value and the ith second intermediate check code to obtain the (i+1)th second intermediate check code;

[0028] The (i+1)th second intermediate check code is calculated to obtain the read check code.

[0029] In some embodiments, the write verification instruction further includes a second memory address;

[0030] The write control module is further configured to write the write check code into the first memory based on the second memory address.

[0031] In some embodiments, the write verification instruction further includes the ID of the second memory;

[0032] The write control module is further configured to write the write check code into the second memory based on the ID of the second memory.

[0033] In some embodiments, the comparison result is that the write check code and the read check code are the same; or the write check code and the read check code are not the same.

[0034] The comparison of the write checksum and the read checksum to obtain the comparison result includes:

[0035] Compare the write checksum and the read checksum. If the write checksum and the read checksum are the same, then the read data block is normal.

[0036] If the write checksum is inconsistent with the read checksum, then the read data block is abnormal.

[0037] According to a second aspect of the embodiments of this application, a method for verifying stored data is provided, comprising:

[0038] Acquire write data instructions and write verification instructions; the write verification instructions include a read address;

[0039] In response to the write data instruction, the data block to be written is written to the first memory;

[0040] In response to the write verification instruction, a data block to be read is obtained based on the read address; the read address and the data block to be read are calculated to obtain a write verification code; the data block to be read is a part of the data block to be written.

[0041] Obtain the read verification instruction; the read verification instruction includes the read address;

[0042] In response to the read verification instruction, the read data block is retrieved from the first memory based on the read address; the read address and the read data block are calculated to obtain a read verification code; the write verification code and the read verification code are compared to obtain a comparison result; the comparison result indicates whether the read data block is abnormal.

[0043] According to a third aspect of the present application, a computer device is provided, the computer device including a processor and a memory, the memory being used to store at least one program, the at least one program being loaded by the processor and executed to verify the stored data method.

[0044] According to a fourth aspect of the embodiments of this application, a computer-readable storage medium is provided, wherein at least one program is stored in the computer-readable storage medium, the at least one program being loaded and executed by a processor to implement the method for verifying stored data.

[0045] In this embodiment, when the data block to be read is part of the data block to be written, when writing the data block to be read to the first memory, the data block to be read is obtained, and the read address corresponding to the data block to be read is calculated to obtain a write check code; the data block to be read in the first memory is obtained, the data block to be read and the read address are calculated to obtain a read check code, and the write check code and read check code are compared to determine whether the data block to be read is abnormal. Compared with ECC in related technologies, the write check code and read check code in this embodiment reduce the storage area and storage bandwidth occupied; in addition, the embodiments of this application also solve the problem of CRC algorithm failure in related technologies, ensuring that the read data used by the ADAS chip is normal, thereby ensuring the safe operation and performance of the ADAS chip, and thus improving the user experience. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 This is a schematic diagram of an implementation environment provided according to an embodiment of this application;

[0048] Figure 2 This is a schematic diagram of the memory framework of an ADAS chip provided by related technologies;

[0049] Figure 3A This is the first illustration provided by related technologies showing that the data block to be written and the data block to be read are inconsistent;

[0050] Figure 3B This is a schematic diagram illustrating the second type of inconsistency between the data block to be written and the data block to be read, provided by related technologies;

[0051] Figure 3C This is a schematic diagram illustrating the third type of inconsistency between the data block to be written and the data block to be read, provided by related technologies;

[0052] Figure 4 This is a schematic diagram of the structure of a controller for verifying stored data according to an embodiment of this application;

[0053] Figure 5 This is a flowchart illustrating a method for calculating and writing a checksum by a controller that verifies stored data, according to an embodiment of this application.

[0054] Figure 6 This is a schematic diagram of the structure of a controller for verifying stored data according to an embodiment of this application;

[0055] Figure 7 This is a flowchart illustrating step S505 according to an embodiment of this application;

[0056] Figure 8 This is a flowchart illustrating a method for calculating and reading a checksum by a controller that verifies stored data, according to an embodiment of this application.

[0057] Figure 9 This is a flowchart illustrating step S803 according to an embodiment of this application.

[0058] Figure 10 This is a schematic diagram of the structure of a controller for verifying and storing data according to an embodiment of this application;

[0059] Figure 11 This is a flowchart illustrating a method for verifying stored data according to an embodiment of this application;

[0060] Figure 12 This is a schematic diagram of the structure of a terminal according to an embodiment of this application;

[0061] Figure 13 This is a schematic diagram of the structure of a server according to an embodiment of this application. Detailed Implementation

[0062] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0063] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application.

[0064] In this application, the terms "first," "second," etc., are used to distinguish identical or similar items that have essentially the same function. It should be understood that there is no logical or temporal dependency between "first," "second," and "nth," nor does it limit the quantity or execution order. It should also be understood that although the following description uses the terms "first," "second," etc., to describe various elements, these elements should not be limited by the terms.

[0065] These terms are simply used to distinguish one element from another. For example, without departing from the scope of various examples, the first action can be called the second action, and similarly, the second action can be called the first action. Both the first and second actions can be actions, and in some cases, they can be separate and distinct actions.

[0066] "At least one" refers to one or more actions. For example, at least one action can be one action, two actions, three actions, or any integer number of actions greater than or equal to one. "Multiple" refers to two or more actions. For example, multiple actions can be two actions, three actions, or any integer number of actions greater than or equal to two.

[0067] Figure 1 This is a schematic diagram of an implementation environment provided according to an embodiment of this application. The implementation environment may include an ADAS chip 101 and a server 102.

[0068] The ADAS chip 101 includes a controller for verifying and storing data.

[0069] Server 102 can be a single server, a server cluster consisting of multiple servers, or a cloud processing center.

[0070] ADAS chip 101 interacts with server 102 through intermediate modules such as vehicle gateway and external network to realize map updates, algorithm evolution, remote maintenance, etc.

[0071] In some embodiments, the external network is a wireless or wired network. The wireless or wired network uses standard communication technologies and / or protocols. The network is typically the Internet, but can be any network, including but not limited to a Local Area Network (LAN), Metropolitan Area Network (MAN), Wide Area Network (WAN), mobile, wired or wireless networks, private networks, or any combination of virtual private networks. In some embodiments, technologies and / or formats including Hyper Text Markup Language (HTML), Extensible Markup Language (XML), etc., are used to represent data exchanged over the network. Furthermore, conventional encryption technologies such as Secure Socket Layer (SSL), Transport Layer Security (TLS), Virtual Private Network (VPN), and Internet Protocol Security (IPsec) can be used to encrypt all or some links. In other embodiments, custom and / or dedicated data communication technologies may be used to replace or supplement the aforementioned data communication technologies.

[0072] Figure 2 This is a schematic diagram of the memory framework of an ADAS chip provided by related technologies. Combined with... Figure 1 The memory framework of the ADAS chip is described in detail.

[0073] ADAS chips include SoC chips. SoC chips include image signal processors (ISPs) and neural network processors.

[0074] The system includes a Neural Processing Unit (NPU), Computer Vision (CV), and multiple Static Random-Access Memory (SRAMs). Direct Memory Access (DMA) is integrated into the ISP, NPU, and CV systems, and is used for data exchange with the SRAM.

[0075] ADAS chips also include Dynamic Random Access Memory (DRAM) and High Bandwidth Memory (HBM).

[0076] In some examples, DMA uses ECC or CRC to protect the data stored in SRAM, DRAM, or HBM.

[0077] For example, when using ECC to protect a block of data to be written, an ECC will be generated that is 1 / 8 the size of the block of data to be written. Transmitting this ECC requires a large amount of memory bandwidth, and storing this ECC also requires a large amount of storage area. As a result, the ECC affects the safe operation and performance of the ADAS chip and reduces the user experience.

[0078] Figures 3A to 3C This is a diagram illustrating three types of inconsistencies between the data blocks to be written and the data blocks to be read, provided by related technologies. (Combined with...) Figures 3A to 3C A detailed explanation is provided for situations where the data block to be written is inconsistent with the data block to be read.

[0079] In some examples, the size of the data block to be written is inconsistent with the size of the data block to be read, that is, the data block to be read is part of the data block to be written. In such scenarios, the CRC algorithm will fail, and the CRC algorithm will be unable to determine whether the read data block obtained from the first memory is abnormal, which will affect the safe operation and performance of the ADAS chip and reduce the user experience.

[0080] To address the aforementioned technical problems, embodiments of this application provide a controller for verifying stored data. When writing a data block to be written to a first memory, the controller retrieves the data block to be read from the data block to be written, calculates the data block to be read and its corresponding read address, and obtains a write checksum. After retrieving the data block to be read from the first memory, the controller calculates the data block to be read and its read address to obtain a read checksum. The write checksum and read checksum are used to determine if the data block to be read is abnormal. If the data block to be read is normal, it is output, and the ADAS chip uses it. If the data block to be read is abnormal, an interrupt signal is generated to alert the ADAS chip to enter a safe state; for example, to remind the driver to exit autonomous driving or downgrade mode. Embodiments of this application verify the abnormality of the data block to be read using write checksums and read checksums, ensuring that the data blocks used by the ADAS chip are normal, thereby guaranteeing the normal operation and performance of the ADAS chip, ultimately ensuring user safety and improving user experience.

[0081] Figure 4 This is a schematic diagram of the structure of a controller for verifying and storing data according to an embodiment of this application. (Combined with...) Figure 4 The structure of the controller for verifying stored data is described in detail. The controller includes: a configuration module 401, a write control module 402, a write verification module 403, and a read verification module 404.

[0082] In some examples, a linked list is provided in configuration module 401; multiple commands are stored in the linked list.

[0083] For example, configuration module 401 is connected to Double Data Rate Synchronous Dynamic Random Access Memory.

[0084] The (Double Data Rate Synchronous Dynamic Random-Access Memory, DDR) is electrically connected, and the configuration module 401 obtains multiple commands from the DDR; these commands are pre-configured.

[0085] For example, configuration module 401 is implemented based on a storage linked list item state machine.

[0086] For example, the controller 400 for verifying stored data is implemented based on DMA.

[0087] Figure 5 This is a flowchart illustrating a method for calculating and writing checksums by a controller that verifies stored data, according to an embodiment of this application. (In conjunction with...) Figure 5 The method for calculating the write check code is described in detail. The method for calculating the write check code includes the following steps S501 to S506.

[0088] In step S501, the configuration module 401 obtains the write data instruction and the write verification instruction.

[0089] The write verification instruction includes reading the address. Write data instructions and write verification instructions are stored in a memory linked list.

[0090] In step S502, the configuration module 401 sends a write data instruction to the write control module 402 to configure the write control module 402.

[0091] For example, the write data instruction includes a write address; the write address includes a start write address and an end write address; the start write address and the end write address indicate a first memory address range corresponding to the data block to be written.

[0092] It is important to understand that the read data block is the data block read from the first memory 500 based on the read address; the data block to be read is the data block that has not yet been written to the first memory 500; the read data block and the data block to be read correspond to the same data block to be written and the same read address; that is, when the read data block is normal, the read data block and the data block to be read are completely identical; however, when the read data block is abnormal, there is a difference between the read data block and the data block to be read. The embodiments of this application are based on this principle to verify whether the read data block is abnormal.

[0093] In some examples, after the write control module 402 completes the configuration, it sends a configuration completion signal to the configuration module 401 to notify the configuration module 401 and waits for the configuration module 401 to send the next command.

[0094] Figure 6 This is a schematic diagram of the structure of a controller for verifying stored data according to an embodiment of this application. (In conjunction with...) Figure 6 The structure of the controller for verifying and storing data is described in detail.

[0095] In step S503, the write control module 402 responds to the write data command and writes the data block to be written into the first memory 500.

[0096] For example, the write control module 402 starts in response to a write data instruction and obtains multiple first memory addresses based on the read address. The write verification module 403 starts in response to a write verification instruction and obtains multiple first memory addresses based on the read address. The write control module 402 and the write verification module 403 can start simultaneously.

[0097] For example, the data block to be written includes multiple data to be written, each data to be written corresponding to a first storage address; in response to the write data instruction, the write control module 402 writes the data to be written corresponding to each first storage address into the first memory 500.

[0098] For example, when the write address indicates the first memory address range corresponding to the data block to be written, the write control module 402 writes the data block to be written into the first memory 500 in one write operation according to the write address.

[0099] For example, when the write address indicates a first memory address range corresponding to a sub-block of data to be written, the block of data to be written may also be divided into multiple sub-blocks of data to be written, each sub-block of data to be written including at least one piece of data to be written; the write control module 402 writes a sub-block of data to be written into the first memory 500 in a single write operation according to the write address. Similarly, a block of data to be read may include multiple sub-blocks of data to be read. Each sub-block of data to be read includes at least one piece of data to be read.

[0100] For example, the size of the data block to be written is 500MB, and the size of each sub-data block to be written is 20MB. The size of the data block to be read is 400MB, and the size of each sub-data block to be written is 16MB.

[0101] For example, the first cache 405 in the controller 400 for verifying stored data is electrically connected to the first memory 500 via a first physical line. The write control module 402 is electrically connected to the first memory 500 via a second physical line.

[0102] For example, the data block to be written output by the NPU is stored in the first cache 405. That is, during the process of the write control module 402 writing the data block to be written to the first memory 500, there is a continuous write data flow between the first cache 405 and the first memory 500.

[0103] For example, in response to a write data command, the write control module 402 sends the data block to be written to the first memory 500 through the first physical line and sends the write address to the first memory 500 through the second physical line.

[0104] For example, the first memory 500 is a cache or memory. For instance, the first memory 500 is DDR.

[0105] In some examples, before the write control module 402 writes the data block to be written to the first memory 500, it determines whether the data block to be written needs to be written to the first memory 500. If the data block to be written needs to be written to the first memory 500, then the data block to be written needs to be verified, that is, the method of verifying stored data needs to be executed. Or if the data block to be written does not need to be written to the first memory 500, then the data block to be written does not need to be verified, that is, the method of verifying stored data does not need to be executed.

[0106] In step S504, the write verification module 403 responds to the write verification instruction and obtains the data block to be read based on the read address.

[0107] It's important to understand that for each data block to be written, after writing it to the first memory 500, it's often only necessary to read a portion of the corresponding write data block. That is, the size of the data block to be read is smaller than the size of the corresponding write data block. In this case, there's no need to verify the write data block; only the read data block needs to be verified. Therefore, when generating the write verification code, the write verification module 403 only needs to obtain the read data block from the write data block. For example, the size of the write data block is 500MB, and the size of the read data block is 400MB.

[0108] For example, a write data stream is generated during the process of the write control module 402 writing the data block to be written to the first memory 500.

[0109] For example, the write verification module 403 is electrically connected to the first physical line via a third physical line. The write verification module 403 is electrically connected to the second physical line via a fourth physical line.

[0110] For example, the write verification module 403 obtains the data to be read corresponding to each first storage address from the write data stream based on each first storage address indicated by the read address, thereby obtaining the data block to be read, and storing the data block to be read into the second cache 407.

[0111] For example, the write verification module 403 parses the write data stream in the first physical line and multiple first storage addresses in the second physical line; for each piece of data to be written, it obtains the first storage address of the data to be written; it compares the first storage address of the data to be written with the first storage address of the data to be read, and if the first storage address of the data to be written is consistent with the first storage address of the data to be read, it obtains the data to be read.

[0112] In some examples, the read address includes an initial read address and an ending read address; the initial read address and the ending read address indicate the first memory address range corresponding to the data block to be read; the data block to be read includes at least one piece of data to be read, and the data to be read corresponds one-to-one with the first memory address. For each data block to be read, the initial read address corresponds to the first first memory address of the data block to be read, and the ending read address corresponds to the last first memory address of the data block to be read.

[0113] It should be noted that the initial read address and the final read address of each read address are calculated through a pre-configured read function and configured into the write verification instruction, the read data instruction, and the read verification instruction. The embodiments of this application will not elaborate further.

[0114] In step S505, the write verification module 403 calculates the read address and the data block to be read to obtain the write verification code.

[0115] The data block to be read is a part of the data block to be written.

[0116] In some examples, for instance, a first XOR value is calculated on a per-data-to-read basis, and a write checksum is calculated on a per-data-to-read basis, thereby determining whether the read data block corresponding to each data-to-read block is abnormal.

[0117] Figure 7 This is a flowchart illustrating step S505 according to an embodiment of this application. (In conjunction with...) Figure 7 Step S505 is described in detail below. Step S505 includes the following steps S5051 to S5053.

[0118] In step S5051, the write verification module 403 performs an XOR operation on the (i+1)th data to be read and the first memory address corresponding to the (i+1)th data to be read to obtain the (i+1)th first XOR value.

[0119] Where i is an integer greater than or equal to 1.

[0120] In step S5052, the write verification module 403 performs addition calculation on the (i+1)th first XOR value and the i-th first intermediate check code to obtain the (i+1)th first intermediate check code.

[0121] In step S5053, the write verification module 403 calculates the (i+1)th first intermediate verification code to obtain the write verification code.

[0122] For example, the (i+1)th first XOR value = the (i+1)th data to be read ^ the (i+1)th first memory address.

[0123] The (i+1)th first intermediate check code = the (i+1)th first XOR value + the ith first intermediate check code.

[0124] For example, in order to ensure the accuracy of the written check code, for the (i+1)th data to be read, after calculating the first XOR value of the (i+1)th data to be read, a bitwise AND operation is performed on the (i+1)th first XOR value and the first preset value to ensure the bit width of the (i+1)th first XOR value.

[0125] For example, the first preset value is 0xFFFFFFFF. The (i+1)th first XOR value is calculated as &0xFFFFFFFF to obtain the (i+1)th first value, thus ensuring that the size (bit width) of the (i+1)th first value is 32 bits.

[0126] For example, in order to prevent the write check code from being 0, for the (i+1)th data to be read, the (i+1)th first value, the ith first intermediate check code, and the second preset value are calculated to obtain the (i+1)th first intermediate check code.

[0127] For example, in order to ensure the accuracy of the (i+1)th first intermediate check code, a bitwise AND operation is performed on the first preset value and the (i+1)th first intermediate check value to obtain the (i+1)th first check value.

[0128] For example, the second preset value is 0x1234567;

[0129] The (i+1)th first intermediate check code = (the i-th first check value × the second preset value + the (i+1)th first value) × 0xFFFFFFFF.

[0130] For example, if the data block to be read includes m data items, then after calculating the mth first intermediate checksum, the write verification module 403 outputs the mth first intermediate checksum, which is also the write checksum. m is an integer greater than or equal to i.

[0131] For example, the initial storage address corresponding to the read data block is 0x1000, and the final storage address is 0x100C.

[0132] The first piece of data to be read is 0xA1B2C3D4, the first memory address is 0x1000, and the first XOR value is 0xA1B2D3D4. The first intermediate checksum value is 0xA1B2D3D4.

[0133] The fifth piece of data to be read is 0x11223344, its first memory address is 0x1004, and its XOR value is 0x11222340. The fifth first intermediate checksum value is 0xB2D4F714.

[0134] The ninth piece of data to be read is 0x55667788, the first memory address of the ninth piece is 0x1008, and the XOR value of the ninth piece is 0x55666780. The first intermediate checksum of the ninth piece is 0x083B5E94.

[0135] The twelfth data to be read is 0xDDEEFF00, the twelfth first memory address is 0x100C, and the twelfth XOR value is 0xDDEEEF0C. The twelfth first intermediate check value is 0xE62A4DA0.

[0136] For example, the storage space occupied by writing the checksum is generally small and can be set according to actual needs. Therefore, compared with ECC in related technologies, writing the checksum occupies a much smaller storage space, which not only saves the memory bandwidth occupied in the process of writing the data block to be written to the first memory 500, but also saves storage area.

[0137] For example, the size of the write checksum is generally less than or equal to 32 bits. For instance, if the write checksum size is 16 bits and the size of a sub-block of data to be read corresponding to the write checksum is 1 MB, when using ECC for verification, the size of the ECC corresponding to this sub-block of data to be read is 1 / 8 MB. 16 bits is much smaller than 1 / 8 MB, so the storage space and memory bandwidth occupied by the write checksum in this application are much smaller than those of EEC.

[0138] In step S506, after obtaining the write verification code, the write verification module 403 notifies the write control module 402, and the write control module 402 writes the write verification code into the first memory 500 or the second memory.

[0139] In some examples, the write verification instruction also includes a second memory address to facilitate the storage of the write verification code;

[0140] For example, the write control module 402 writes the write check code to the first memory 500 based on the second memory address. That is, the data block to be written and the corresponding write check code are both stored in the first memory 500.

[0141] In other examples, in order to determine the storage location of the write check code and facilitate subsequent retrieval of the write check code's storage location, the write check instruction in the embodiments of this application further includes an identifier (ID) of the second memory.

[0142] For example, the write control module 402 writes the write check code into the second memory based on the ID of the second memory.

[0143] For example, the write verification module 403 includes a second memory. The write verification module 403 writes the write verification code into the second memory using the ID of the second memory. For example, the second memory is a memory with a storage space of 1k.

[0144] Figure 8This is a flowchart illustrating a method for calculating and reading a checksum by a controller that verifies stored data, according to an embodiment of this application. (In conjunction with...) Figure 8 The method for calculating the read check code is described in detail. The method for calculating the read check code includes the following steps S801 to S804.

[0145] In step S801, the configuration module 401 obtains a read verification instruction; the read verification instruction includes a read address.

[0146] In some examples, configuration module 401 sends a read verification command to read verification module 404 to configure read verification module 404.

[0147] In step S802, the read verification module 404 responds to the read verification instruction and retrieves the read data block from the first memory 500 based on the read address.

[0148] For example, the read verification module 404 obtains multiple first memory addresses by reading the address.

[0149] In step S803, the read verification module 404 calculates the read address and reads the data block to obtain the read verification code.

[0150] In some examples, the read data block includes at least one read data; the read data corresponds one-to-one with a first memory address.

[0151] In some examples, in order to determine the storage location of the read verification code and facilitate subsequent retrieval of the read verification code's storage location, the read verification instruction in the embodiments of this application also includes the ID of a third memory.

[0152] For example, the read control module 406 writes the read verification code into the third memory based on the ID of the third memory.

[0153] For example, the read verification module 404 includes a third memory. The read verification module 404 writes the read verification code into the third memory using the ID of the third memory. For example, the third memory is a memory with a storage space of 1k.

[0154] Figure 9 This is a flowchart illustrating step S803 according to an embodiment of this application. (In conjunction with...) Figure 9 The following is a detailed description of step S803. Step S803 includes the following steps S8031 to S8033.

[0155] In step S8031, the read verification module 404 performs an XOR operation on the (i+1)th read data and the first memory address corresponding to the (i+1)th read data to obtain the (i+1)th second XOR value.

[0156] In step S8032, the read verification module 404 performs addition calculation on the (i+1)th second XOR value and the i-th second intermediate check code to obtain the (i+1)th second intermediate check code.

[0157] In step S8033, the read verification module 404 calculates the (i+1)th second intermediate check code to obtain the read verification code.

[0158] For example, the (i+1)th second XOR value = the (i+1)th read data ^ the (i+1)th first memory address.

[0159] The (i+1)th second intermediate check code = the (i+1)th second XOR value + the ith second intermediate check code.

[0160] It should be noted that the specific method for calculating the read check code is the same as the specific method for calculating the write check code. Therefore, the specific method for calculating the write check code in the above embodiments can be used to calculate the read check code, and the embodiments of this application will not be described again.

[0161] Figure 10 This is a schematic diagram of the structure of a controller for verifying and storing data according to an embodiment of this application. (In conjunction with...) Figure 10 The structure of the controller for verifying and storing data is described in detail.

[0162] In some examples, the controller also includes a read control module 406.

[0163] During the process of reading the read data block, the read control module 406 generates a read data stream.

[0164] For example, configuration module 401 obtains a read data instruction; the read data instruction includes a read address; read control module 406 responds to the read data instruction and reads a read data block from the first memory 500 based on the read address; read verification module 404 responds to the read verification instruction and obtains a read data block from the read data stream based on the read address.

[0165] For example, the read control module 406 obtains multiple first memory addresses by reading the addresses.

[0166] For example, the read control module 406 is electrically connected to the first memory 500 through the fifth physical line and the sixth physical line; the read verification module 404 is electrically connected to the fifth physical line through the seventh physical line; and the read verification module 404 is electrically connected to the sixth physical line through the eighth physical line.

[0167] For example, the read control module 406 sends multiple first memory addresses to the first memory 500 through the fifth physical line and obtains multiple read data through the sixth physical line.

[0168] In step S804, the read verification module 404 compares the write verification code and the read verification code to obtain the comparison result; the comparison result indicates whether the read data block is abnormal.

[0169] In some examples, a comparator is provided in the read verification module 404, which is electrically connected to the second memory and the third memory, and is used to compare the write check code and the read check code.

[0170] In some examples, the comparison result is that the write checksum matches the read checksum; or the write checksum does not match the read checksum.

[0171] For example, the write checksum and the read checksum are compared. If the write checksum and the read checksum are the same, then the read data block and the data block to be read are the same, that is, the read data block is normal, and the comparator notifies the ADAS chip.

[0172] For example, if the write check code and the read check code are inconsistent, then the read data block and the data block to be read are inconsistent. The read data block has changed compared to the data block to be read, that is, the read data block is abnormal, and the comparator sends an interrupt signal to the ADAS chip.

[0173] In some embodiments, by comparing the write checksum and the read checksum, the diagnostic coverage is improved, thereby improving the accuracy of determining whether the read data block is abnormal.

[0174] For example, the third preset value, the preset coefficient, and m are calculated to obtain the diagnostic coverage rate.

[0175] For example, the third preset value is 1, and the preset coefficient is...

[0176]

[0177] When the size of the data block being read is 1MB, then m is 10. 4 The diagnostic coverage rate was 99.9%.

[0178] When the size of the data block being read is 10MB, then m is 10. 4 The diagnostic coverage rate was 98.5%.

[0179] In ADAS chips, each read data block is less than 10MB. The functional safety requirement for ASILB (Automotive Safety Integrity Level B) is a diagnostic coverage of greater than 90%. Therefore, the embodiments of this application meet the functional safety requirements of ASILB. ASILB is one of the automotive safety integrity levels defined in the ISO 26262 standard.

[0180] It should be noted that the controller for verifying and storing data provided in the above embodiments is only illustrated by the division of the above functional modules when performing the corresponding steps. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0181] In embodiments of this application, when the data block to be read is part of the data block to be written, when writing the data block to be read into the first memory, the data block to be read is obtained, and the read address corresponding to the data block to be read is calculated to obtain a write check code; the data block to be read in the first memory is obtained, the data block to be read and the read address are calculated to obtain a read check code, and by comparing the write check code and the read check code, it is determined whether the data block to be read is abnormal. Compared with ECC in related technologies, the write check code and read check code in the embodiments of this application reduce the storage area and storage bandwidth occupied; in addition, the embodiments of this application also solve the problem of CRC algorithm failure in related technologies, ensuring that the read data used by the ADAS chip is normal, thereby ensuring the safe operation and performance of the ADAS chip, and thus improving the user experience.

[0182] Figure 11 This is a flowchart illustrating a method for verifying stored data according to an embodiment of this application. Figure 11 The method for verifying stored data is described in detail below. This method includes the following steps:

[0183] In step S1101, a write data instruction and a write verification instruction are obtained; the write verification instruction includes a read address.

[0184] In step S1102, in response to the write data instruction, the data block to be written is written to the first memory;

[0185] In step S1103, in response to the write verification instruction, the data block to be read is obtained based on the read address; the read address and the data block to be read are calculated to obtain the write verification code.

[0186] The data block being read is a part of the data block to be written;

[0187] In step S1104, a read verification instruction is obtained; the read verification instruction includes a read address;

[0188] In step S1105, in response to the read verification instruction, a read data block is obtained from the first memory based on the read address; the read address and the read data block are calculated to obtain the read verification code; the write verification code and the read verification code are compared to obtain the comparison result.

[0189] The comparison result indicates whether the read data block is abnormal.

[0190] In some embodiments, a write data stream is generated during the process of the write control module writing the data block to be written to the first memory;

[0191] The write verification module obtains the data block to be read based on the read address, including;

[0192] The write verification module obtains the data block to be read from the write data stream based on the read address.

[0193] In some embodiments, the read address includes an initial read address and an end read address; the initial read address and the end read address indicate a first memory address range corresponding to the data block to be read; the data block to be read includes at least one data to be read, and the data to be read corresponds one-to-one with the first memory address.

[0194] Calculate the read address and the data block to be read to obtain the write checksum, including:

[0195] Perform an XOR operation on the (i+1)th data to be read and the first memory address corresponding to the (i+1)th data to be read to obtain the (i+1)th first XOR value; i is an integer greater than or equal to 1;

[0196] Add the (i+1)th first XOR value and the ith first intermediate check code to obtain the (i+1)th first intermediate check code;

[0197] Calculate the (i+1)th first intermediate check code to obtain the write check code.

[0198] In some embodiments, the controller further includes a read control module;

[0199] The configuration module is also used to obtain read data instructions; read data instructions include read addresses;

[0200] The read control module is used to read a data block from the first memory in response to a read data command, based on the read address; wherein, a read data stream is generated during the process of the read control module reading the data block to be read.

[0201] The read verification module is used to retrieve the read data block from the read data stream based on the read address in response to the read verification command.

[0202] In some embodiments, the read data block includes at least one read data; the read data corresponds one-to-one with a first memory address;

[0203] Calculate the read address and read the data block to obtain the read checksum, including:

[0204] Perform an XOR operation on the (i+1)th read data and the first memory address corresponding to the (i+1)th read data to obtain the (i+1)th second XOR value;

[0205] Add the (i+1)th second XOR value and the ith second intermediate check code to obtain the (i+1)th second intermediate check code;

[0206] Calculate the (i+1)th second intermediate check code to obtain the read check code.

[0207] In some embodiments, the write verification instruction further includes a second memory address;

[0208] The write control module is also used to write the write check code into the first memory based on the second memory address.

[0209] In some embodiments, the write verification instruction further includes the ID of the second memory;

[0210] The write control module is also used to write a write check code into the second memory based on the ID of the second memory.

[0211] In some embodiments, the comparison result is that the write check code and the read check code are the same; or the write check code and the read check code are not the same.

[0212] Compare the written checksum and the read checksum to obtain the comparison result, including:

[0213] Compare the write checksum and the read checksum. If the write checksum and the read checksum are the same, then the data block is read normally.

[0214] If the write checksum and the read checksum are inconsistent, then reading the data block will result in an error.

[0215] It should be noted that the controller for verifying stored data and the method for verifying stored data provided in the above embodiments belong to the same concept. For details of their specific implementation process, please refer to the controller embodiment, which will not be repeated here.

[0216] In embodiments of this application, when the data block to be read is part of the data block to be written, when writing the data block to be read into the first memory, the data block to be read is obtained, and the read address corresponding to the data block to be read is calculated to obtain a write check code; the data block to be read in the first memory is obtained, the data block to be read and the read address are calculated to obtain a read check code, and by comparing the write check code and the read check code, it is determined whether the data block to be read is abnormal. Compared with ECC in related technologies, the write check code and read check code in the embodiments of this application reduce the storage area and storage bandwidth occupied; in addition, the embodiments of this application also solve the problem of CRC algorithm failure in related technologies, ensuring that the read data used by the ADAS chip is normal, thereby ensuring the safe operation and performance of the ADAS chip, and thus improving the user experience.

[0217] An embodiment of this application also provides a computer device, including a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein the processor executes the computer program to implement the method described above.

[0218] Taking computer devices as terminals as an example, Figure 12 This is a schematic diagram of the structure of a terminal provided in an embodiment of this application. See also... Figure 12 Terminal 1200 can be: a smartphone, tablet computer, MP3 player (Moving Picture Experts Group Audio Layer III), MP4 player (Moving Picture Experts Group Audio Layer IV), laptop computer, or desktop computer. Terminal 1200 may also be referred to as user equipment, portable terminal, laptop terminal, desktop terminal, or other names.

[0219] Typically, terminal 1200 includes a processor 1201 and a memory 1202.

[0220] Processor 1201 may include one or more processing cores, such as a quad-core processor, a penta-core processor, etc. Processor 1201 may be implemented using at least one hardware form selected from DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). Processor 1201 may also include a main processor and a coprocessor. The main processor, also known as a CPU (Central Processing Unit), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, processor 1201 may integrate a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, processor 1201 may also include an AI (Artificial Intelligence) processor, which is used to handle computational operations related to machine learning.

[0221] The memory 1202 may include one or more computer-readable storage media, which may be non-transitory. The memory 1202 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In some embodiments, the non-transitory computer-readable storage media in the memory 1202 are used to store at least one program code, which is executed by the processor 1201 to implement the process of terminal execution in the method embodiments of this application.

[0222] In some embodiments, the terminal 1200 may also optionally include a peripheral device interface 1203 and at least one peripheral device. The processor 1201, memory 1202, and peripheral device interface 1203 can be connected via a bus or signal line. Each peripheral device can be connected to the peripheral device interface 1203 via a bus, signal line, or circuit board. Specifically, the peripheral device includes at least one of a display screen 1204, a camera assembly 1205, an audio circuit 1206, and a power supply 1207.

[0223] Peripheral device interface 1203 can be used to connect at least one I / O (Input / Output) related peripheral device to processor 1201 and memory 1202. In some embodiments, processor 1201, memory 1202 and peripheral device interface 1203 are integrated on the same chip or circuit board; in some other embodiments, any one or two of processor 1201, memory 1202 and peripheral device interface 1203 can be implemented on separate chips or circuit boards, and this application embodiment does not limit this.

[0224] Display screen 1204 is used to display a UI (User Interface). This UI may include graphics, text, icons, videos, and any combination thereof. When display screen 1204 is a touch display screen, it also has the ability to collect touch signals on or above its surface. These touch signals can be input as control signals to processor 1201 for processing. In this case, display screen 1204 can also be used to provide virtual buttons and / or a virtual keyboard, also known as soft buttons and / or a soft keyboard. In some embodiments, there may be one display screen 1204, disposed on the front panel of terminal 1200; in other embodiments, there may be at least two display screens, disposed on different surfaces of terminal 1200 or in a folded design; in still other embodiments, display screen 1204 may be a flexible display screen, disposed on a curved or folded surface of terminal 1200. Furthermore, display screen 1204 may be configured as a non-rectangular, irregular shape, i.e., a non-rectangular screen. The display screen 1204 can be made of materials such as LCD (Liquid Crystal Display) and OLED (Organic Light-Emitting Diode).

[0225] The camera assembly 1205 is used to acquire images or videos. In some embodiments, the camera assembly 1205 includes a front-facing camera and a rear-facing camera. Typically, the front-facing camera is located on the front panel of the terminal, and the rear-facing camera is located on the back of the terminal. In some embodiments, there are at least two rear-facing cameras, which are any one of a main camera, a depth-sensing camera, a wide-angle camera, and a telephoto camera, to achieve background blurring by fusion of the main camera and the depth-sensing camera, panoramic shooting by fusion of the main camera and the wide-angle camera, VR (Virtual Reality) shooting, or other fusion shooting functions. In some embodiments, the camera assembly 1205 may also include a flash. The flash can be a single-color temperature flash or a dual-color temperature flash. A dual-color temperature flash refers to a combination of a warm light flash and a cool light flash, which can be used for light compensation at different color temperatures.

[0226] The audio circuit 1206 may include a microphone and a speaker. The microphone is used to collect sound waves from the user and the environment, and convert the sound waves into electrical signals which are then input to the processor 1201 for processing. For stereo sound acquisition or noise reduction purposes, multiple microphones may be used, each positioned at a different location on the terminal 1200. The microphone may also be an array microphone or an omnidirectional microphone. The speaker is used to convert the electrical signals from the processor 1201 into sound waves. The speaker may be a conventional diaphragm speaker or a piezoelectric ceramic speaker. When the speaker is a piezoelectric ceramic speaker, it can convert electrical signals not only into audible sound waves but also into inaudible sound waves for purposes such as distance measurement. In some embodiments, the audio circuit 1206 may also include a headphone jack.

[0227] Power supply 1207 is used to power the various components in terminal 1200. Power supply 1207 can be AC ​​power, DC power, a disposable battery, or a rechargeable battery. When power supply 1207 includes a rechargeable battery, the rechargeable battery can support wired charging or wireless charging. The rechargeable battery can also be used to support fast charging technology.

[0228] Those skilled in the art will understand that Figure 12 The structure shown does not constitute a limitation on terminal 1200 and may include more or fewer components than shown, or combine certain components, or use different component arrangements.

[0229] Taking computer equipment as a server as an example, Figure 13 This is a schematic diagram of a server structure provided in an embodiment of this application. The server 1300 can vary significantly due to different configurations or performance. It may include one or more Central Processing Units (CPUs) 1301 and one or more memories 1302. Each memory 1302 stores at least one computer program, which is loaded and executed by the one or more processors 1301 to implement the aforementioned method for verifying stored data. Of course, the server 1300 may also have wired or wireless network interfaces, a keyboard, and input / output interfaces for input / output. The server 1300 may also include other components for implementing device functions, which will not be elaborated upon here.

[0230] Embodiments of this application also provide a computer-readable storage medium, which includes a stored computer program, wherein the computer program, when running, controls the device where the computer-readable storage medium is located to perform the method described above. Optionally, the computer-readable storage medium may be read-only memory (ROM), random access memory (RAM), compact-disc read-only memory (CD-ROM), magnetic tape, floppy disk, and optical data storage device, etc.

[0231] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0232] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A controller for verifying stored data, characterized in that, include: The configuration module is used to obtain write data instructions and write verification instructions; the write verification instructions include a read address. A write control module is used to write the data block to be written into the first memory in response to the write data command; The write verification module is used to obtain the data block to be read based on the read address in response to the write verification command; Calculate the read address and the data block to be read to obtain the write check code; The data block to be read is a part of the data block to be written; The configuration module is further configured to obtain a read verification instruction; the read verification instruction includes the read address; A read verification module is used to retrieve a read data block from the first memory based on the read address in response to the read verification instruction; Calculate the read address and the read data block to obtain the read check code; The write check code and the read check code are compared to obtain the comparison result; The comparison result indicates whether the read data block is abnormal.

2. The controller according to claim 1, characterized in that, During the process of the write control module writing the data block to be written into the first memory, a write data stream is generated. The write verification module obtains the data block to be read based on the read address, including: The write verification module obtains the data block to be read from the write data stream based on the read address.

3. The controller according to claim 1, characterized in that, The read address includes an initial read address and an end read address; the initial read address and the end read address indicate the first memory address range corresponding to the data block to be read; the data block to be read includes at least one piece of data to be read, and the data to be read corresponds one-to-one with the first memory address. The step of calculating the read address and the data block to be read to obtain the write verification code includes: Perform an XOR operation on the (i+1)th piece of data to be read and the first memory address corresponding to the (i+1)th piece of data to be read to obtain the (i+1)th first XOR value; i is an integer greater than or equal to 1; Add the (i+1)th first XOR value and the ith first intermediate check code to obtain the (i+1)th first intermediate check code; The write check code is obtained by calculating the (i+1)th first intermediate check code.

4. The controller according to claim 1, characterized in that, The controller also includes a read control module; The configuration module is further configured to acquire a read data instruction; the read data instruction includes the read address; The read control module is configured to read the read data block from the first memory based on the read address in response to the read data instruction; wherein a read data stream is generated during the process of the read control module reading the data block to be read. The read verification module is used to respond to the read verification instruction and obtain the read data block from the read data stream based on the read address.

5. The controller according to claim 1, characterized in that, The read data block includes at least one read data; The read data corresponds one-to-one with the address of the first memory; The calculation of the read address and the read data block to obtain the read check code includes: Perform an XOR operation on the (i+1)th read data and the first memory address corresponding to the (i+1)th read data to obtain the (i+1)th second XOR value; Add the (i+1)th second XOR value and the ith second intermediate check code to obtain the (i+1)th second intermediate check code; The (i+1)th second intermediate check code is calculated to obtain the read check code.

6. The controller according to claim 1, characterized in that, The write verification instruction also includes a second memory address; The write control module is further configured to write the write check code into the first memory based on the second memory address.

7. The controller according to claim 1, characterized in that, The write verification instruction also includes the ID of the second memory; The write control module is further configured to write the write check code into the second memory based on the ID of the second memory.

8. The controller according to any one of claims 1 to 7, characterized in that, The comparison result is that the write check code and the read check code are consistent; Or the write check code is inconsistent with the read check code; The comparison of the write checksum and the read checksum to obtain the comparison result includes: Compare the write checksum and the read checksum. If the write checksum and the read checksum are the same, then the read data block is normal. If the write checksum is inconsistent with the read checksum, then the read data block is abnormal.

9. A method for verifying stored data, characterized in that, include: Acquire write data instructions and write verification instructions; the write verification instructions include a read address; In response to the write data instruction, the data block to be written is written to the first memory; In response to the write verification instruction, the data block to be read is obtained based on the read address; Calculate the read address and the data block to be read to obtain the write check code; The data block to be read is a part of the data block to be written; Obtain the read verification instruction; the read verification instruction includes the read address; In response to the read verification instruction, a read data block is retrieved from the first memory based on the read address; Calculate the read address and the read data block to obtain the read check code; The write check code and the read check code are compared to obtain the comparison result; The comparison result indicates whether the read data block is abnormal.

10. A computer device, characterized in that, The computer device includes a processor and a memory, the memory being used to store at least one program, the at least one program being loaded by the processor and executed as described in claim 9 for verifying stored data.

11. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores at least one program, which is loaded and executed by a processor to implement the method for verifying stored data as described in claim 9.

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