Method and system for RAM fault testing

Abstract

The disclosed memory fault testing method comprises: from the target, selecting at least three address units with same bit width as the memory data bus; writing testing vectors into every selected unit to read the back vector for comparison with the original and final fault decision. This invention can ensure the testing accuracy and precision for embedded communication devices.

Description

technical field [0001] The invention relates to the field of memory testing, in particular to a method and system for testing memory faults in an embedded communication device system. Background technique [0002] As shown in Figure 1: In the embedded communication device system, the processor, memory, bootrom and peripheral I / 0 (input / output) devices constitute a basic system. During the design and manufacture of the system, it is necessary to test the interconnection between the various devices that make up the system and the reliability of the devices themselves to diagnose the faults of the hardware system. There are two types of faults in random access memory (Random-Access Memory, RAM): peripheral interconnection faults and chip internal faults. Among them, the failure of peripheral interconnection can be divided into the failure of data bus, the failure of address bus and the failure of control bus. If the system has a failure of the control bus, the memory will bas...

AI Technical Summary

Problems solved by technology

[0012] Using the above test method to test the failure of the data bus must be under the premise that the tested memory has no memory address bus failure or internal unit failure of the memory. The test result can accurately reflect the failure of the tested memory data bus, but In fact, when the memory address bus is tested by using the test method of the prior art, the fault of the memory address bus or the fault of the internal chip of the memory cannot be ruled out, and a sufficient basis for judging the accuracy of the data bus test cannot be provided.

Therefore, it will lead to unreliable results of subsequent address bus fault tests and memory internal unit fault tests.

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