Bad Column Management with Bit Information in Non-Volatile Memory Systems

a non-volatile memory and column management technology, applied in static storage, digital storage, instruments, etc., can solve the problems of unsuitable mobile and handheld environment, bulky disk drives, and easy mechanical failures,

Inactive Publication Date: 2011-01-06
SANDISK TECH LLC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0042]A non-volatile memory circuit including an array of non-volatile memory cells formed along columns of multiple bits, the columns including a plurality of regular columns and one or more redundancy columns, is described. The memory circuit also includes a plurality of latches, each corresponding to one of the regular columns and having a bit whose value indicates if the corresponding column is defective. The m

Problems solved by technology

Conventional mass storage, based on rotating magnetic medium such as hard drives and floppy disks, is unsuitable for the mobile and handheld environment.
This is because disk drives tend to be bulky, are prone to mechanical failure and have high latency and high power requirements.
These undesirable attributes make disk-based storage impractical in most mobile and portable applications.
It is often difficult to perform both of these functions in an optimum manner with a single voltage.
Programming of charge storage memory devices can only result in adding more charge to its charge storage elements.
However, as can be seen from FIG. 6A, the circuitry of a read/write module will likely be implemented with many more transistors and circuit elements and therefore will occupy a space over many columns.
However, the interleaving page architecture is disadvantageous in at least t

Method used

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  • Bad Column Management with Bit Information in Non-Volatile Memory Systems
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  • Bad Column Management with Bit Information in Non-Volatile Memory Systems

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Embodiment Construction

[0076]FIG. 7A illustrates schematically a compact memory device having a bank of partitioned read / write stacks, in which the improved processor of the present invention is implemented. The memory device includes a two-dimensional array of memory cells 300, control circuitry 310, and read / write circuits 370. The memory array 300 is addressable by word lines via a row decoder 330 and by bit lines via a column decoder 360. The read / write circuits 370 is implemented as a bank of partitioned read / write stacks 400 and allows a block (also referred to as a “page”) of memory cells to be read or programmed in parallel. In a preferred embodiment, a page is constituted from a contiguous row of memory cells. In another embodiment, where a row of memory cells are partitioned into multiple blocks or pages, a block multiplexer 350 is provided to multiplex the read / write circuits 370 to the individual blocks.

[0077]The control circuitry 310 cooperates with the read / write circuits 370 to perform memo...

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PUM

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Abstract

Column based defect management techniques are presented. Each column of the memory has an associated isolation latch or register whose value indicates whether the column is defective, but in addition to this information, for columns marked as defective, additional information is used to indicate whether the column as a whole is to be treated as defective, or whether just individual bits of the column are defective. The defective elements can then be re-mapped to a redundant element at either the appropriate bit or column level based on the data. When a column is bad, but only on the bit level, the good bits can still be used for data, although this may be done at a penalty of under programming for some bits, as is described further below. A self contained Built In Self Test (BIST) flow constructed to collect the bit information through a set of column tests is also described. Based on this information, the bad bits can be extracted and re-grouped into bytes by the controller or on the memory to more efficiently use the column redundancy area.

Description

FIELD OF THE INVENTION[0001]This invention relates generally to non-volatile semiconductor memory such as electrically erasable programmable read-only memory (EEPROM) and flash EEPROM and, more specifically, to techniques for handling defects in such memories.BACKGROUND OF THE INVENTION[0002]Solid-state memory capable of nonvolatile storage of charge, particularly in the form of EEPROM and flash BEPROM packaged as a small form factor card, has recently become the storage of choice in a variety of mobile and handheld devices, notably information appliances and consumer electronics products. Unlike RAM (random access memory) that is also solid-state memory, flash memory is non-volatile, retaining its stored data even after power is turned off. In spite of the higher cost, flash memory is increasingly being used in mass storage applications. Conventional mass storage, based on rotating magnetic medium such as hard drives and floppy disks, is unsuitable for the mobile and handheld envir...

Claims

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Application Information

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IPC IPC(8): G11C16/06G11C29/00G11C7/10G11C16/04
CPCG11C29/808G11C29/00G11C16/10
Inventor LI, YANKIM, KWANG-HOTSAI, FRANK W.BOTTELLI, ALDO
Owner SANDISK TECH LLC
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