Method for establishing network chip module level function checking testing platform

A test platform and network chip technology, applied in special data processing applications, instruments, electrical digital data processing, etc., can solve problems such as huge workload and time-consuming, and achieve the effect of clear structure, reduced setup time, and easy to understand

Active Publication Date: 2008-05-21
苏州盛科科技有限公司
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Problems solved by technology

It solves the defects that the existing high-performance network chips nee...

Method used

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  • Method for establishing network chip module level function checking testing platform

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Embodiment Construction

[0041] Most of the steps of the establishment method of the network chip module-level function verification test platform are completed by using the perl language.

[0042] First create a register table file based on all externally accessible registers of the module under test. The register table file should include: address of the register, read / write type, data bit width of the register, valid bits of the register and initial value of the register. This step is done manually according to the definition of the register.

[0043] Use the perl language to read the register table file line by line, and generate the register initialization module and register configuration file according to the register name and initial value;

[0044] Using the perl language, according to the syntax of the hardware description language, the instantiation of the tested module is generated according to each input and output port of the tested module;

[0045] Use perl language to give different v...

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Abstract

The invention relates to a method for constructing a verification and test platform of network chip module level functions, comprising the construction of a simulation and reference model of the tested modules, which is characterized in that: the method comprises the construction of all modules and documents; the output of an excitation generating model is connected with the inputs of the tested module and the simulation and reference model, a clock and a reset generating module are connected with the tested module and the clock and reset signal of the simulation and reference model, a register initialization module is connected with the register of the tested module and the simulation and reference model, and a CPU simulation module is connected with the CPU of the tested module; the output of the tested module is connected with the simulation and reference model, thus, the network chip module level function verification and test platform can be constructed. The invention has the advantages that the platform can be constructed easily and directly, so the time required to construct the module level function verification and test platform can be shortened greatly in the high performance network chip verification process; meanwhile, the platform constructed by the method has clear structure which is easy to be understood and has improved reliability.

Description

technical field [0001] The invention belongs to the field of network chip design verification, and in particular relates to a method for establishing a test platform for module-level function verification in the network chip design process. Background technique [0002] Functional verification of high-performance network chips has become a major bottleneck restricting the design of highly complex electronic systems and chips. With the rapid increase in the number of chip pins and the continuous shrinking of chip size, functional verification has become the primary factor affecting the overall design cost. An efficient functional verification solution requires flexible and effective verification process automation technology and proven verification methods. [0003] For the functional verification process, most chip design companies currently adopt appropriate or more advanced verification platforms, flexibly use various verification methods, improve the usability and reusab...

Claims

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Application Information

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IPC IPC(8): G06F17/50
Inventor 李枫胡国兴郑有为
Owner 苏州盛科科技有限公司
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