UVM environment constructing method and system

An environment and module-under-test technology, applied in the field of general verification methodology, can solve problems such as time-consuming, complex verification environment, and the inability of verification engineers to complete independently, saving time, improving verification efficiency, and reducing verification difficulty.

Active Publication Date: 2018-05-15
BEIJING XIAOMI PINECONE ELECTRONICS CO LTD
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  • Abstract
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Problems solved by technology

[0009] When a design module contains multiple types of interfaces, verification engineers are required to build a very complex process. The resulting verification enviro

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  • UVM environment constructing method and system
  • UVM environment constructing method and system
  • UVM environment constructing method and system

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Embodiment Construction

[0064] Specific embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. It should be understood that the specific embodiments described here are only used to illustrate and explain the present disclosure, and are not intended to limit the present disclosure.

[0065] Such as figure 2 As shown, the overall flowchart of a UVM environment construction method provided by the present invention, the method includes:

[0066] Step S1, according to the interface type of the module under test, configure the components corresponding to the interface through graphic input, the components include at least sequencer, driver and detector monitor, and generate a configuration file of graphic structure;

[0067] Step S2, analyzing the configuration file of the graphic structure to obtain the UVM tree structure and the corresponding UVM environment file;

[0068] Step S3, connecting the module under test for establishing a stand...

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Abstract

The invention relates to a UVM environment constructing method and system, and belongs to the technical field of universal verification methods. The method includes the steps that according to the number and the type of monitored module interfaces, assemblies corresponding to the interfaces are configured in a graphic input mode, wherein each assembly at least comprises a sequencer, a driver and amonitor, and configuration files of graphic structures are generated; the configuration files of the graphic structures are analyzed, and UVM tree structures and corresponding UVM environment files are obtained; monitored modules are connected, and the UVM verification environment is established. The system comprises a configuration module, an analysis module and a calling module. According to UVM environment constructing method and system, the learning difficulty and the development difficulty of verification engineers are reduced, time of developing the verification environment is saved, verification time is shortened, and the verification efficiency is improved.

Description

technical field [0001] The present disclosure relates to Universal Verification Methodology (Universal Verification Methodology, referred to as UVM), in particular, to a UVM environment construction method and system. Background technique [0002] With the improvement of chip performance, the scale of chip design is getting larger and larger, and the reliance on verification is getting higher and higher. In order to cope with more and more complex designs, the verification environment has also changed from the original simple environment to a reusable, object-oriented complex environment. As the verification environment is becoming more and more complex, even professional verifiers need more than 2 weeks to build a complete verification environment. [0003] At present, the verification environment of the chip design module is usually based on the system verilog language or UVM and virtual machine monitor (Virtual Machine Monitor, VMM for short) based on the system verilog ...

Claims

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Application Information

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IPC IPC(8): G06F17/50
CPCG06F30/398G06F30/20
Inventor 孟庆辉
Owner BEIJING XIAOMI PINECONE ELECTRONICS CO LTD
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