UVM environment constructing method and system

Abstract

The invention relates to a UVM environment constructing method and system, and belongs to the technical field of universal verification methods. The method includes the steps that according to the number and the type of monitored module interfaces, assemblies corresponding to the interfaces are configured in a graphic input mode, wherein each assembly at least comprises a sequencer, a driver and amonitor, and configuration files of graphic structures are generated; the configuration files of the graphic structures are analyzed, and UVM tree structures and corresponding UVM environment files are obtained; monitored modules are connected, and the UVM verification environment is established. The system comprises a configuration module, an analysis module and a calling module. According to UVM environment constructing method and system, the learning difficulty and the development difficulty of verification engineers are reduced, time of developing the verification environment is saved, verification time is shortened, and the verification efficiency is improved.

Description

technical field [0001] The present disclosure relates to Universal Verification Methodology (Universal Verification Methodology, referred to as UVM), in particular, to a UVM environment construction method and system. Background technique [0002] With the improvement of chip performance, the scale of chip design is getting larger and larger, and the reliance on verification is getting higher and higher. In order to cope with more and more complex designs, the verification environment has also changed from the original simple environment to a reusable, object-oriented complex environment. As the verification environment is becoming more and more complex, even professional verifiers need more than 2 weeks to build a complete verification environment. [0003] At present, the verification environment of the chip design module is usually based on the system verilog language or UVM and virtual machine monitor (Virtual Machine Monitor, VMM for short) based on the system verilog ...

AI Technical Summary

Problems solved by technology

[0009] When a design module contains multiple types of interfaces, verification engineers are required to build a very complex process. The resulting verification environment is complex and takes a lot of time. Most verification engineers cannot complete it independently, and teamwork is required to complete the verification environment.

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