Training method and application method of circuit encoder, terminal equipment and storage medium

Abstract

The invention is suitable for the technical field of EDA, and provides a training method and an application method of a circuit encoder, terminal equipment and a storage medium, and the training method comprises the steps: respectively converting a register transfer level code and a gate level netlist into graphs, and extracting the features of nodes and the features of edges in the graphs; based on the one-to-one correspondence between the register transfer level codes and register pairs in the gate-level netlist, extracting the register transfer level codes and sub-circuits of each register pair in the gate-level netlist from the graph; a circuit encoder is trained through a self-supervised pre-training task, and an embedded vector of a register transfer-level code and an embedded vector of a gate-level netlist which are aligned across stages in a shared potential space are generated. The embodiment of the invention provides an efficient, universal and accurate circuit encoder, by utilizing the circuit encoder, the processing capability of various different types of EDA tasks based on machine learning can be remarkably improved, and the development process of the tasks is simplified.

Description

Technical Field

[0001] The present application belongs to the technical field of electronic design automation (EDA), and in particular, relates to a training method, an application method, a terminal device and a storage medium of a circuit encoder. Background Art

[0002] As the complexity of integrated circuits increases, EDA tools play a vital role in improving design efficiency and optimizing design quality. In recent years, machine learning (ML) technology has been widely used in the EDA field, and many automated tasks in the design process have been realized through data-driven methods. Existing ML methods are usually developed for specific tasks in EDA design, which means that each design task (for example, timing prediction, area prediction, power estimation, etc.) needs to be built, trained, and optimized separately. This method is not only time-consuming and labor-intensive, but also difficult to reuse existing models and data between multiple tasks. Summary of the invention

[0003] In view of this, the embodiments of the present application provide a training method, an application method, a terminal device and a storage medium for a circuit encoder to solve the problem that the existing machine learning methods need to separately build, train and optimize the corresponding ML model for each EDA design task, which is time-consuming and labor-intensive and difficult to reuse existing models and data between multiple tasks.

[0004] A first aspect of an embodiment of the present application provides a circuit encoder training method, the training method comprising:

[0005] Converting register transfer level code and gate level netlist into graphs respectively, and extracting features of nodes and edges in the graphs;

[0006] extracting from the graph a subcircuit of each register pair in the register transfer level code and the gate level netlist based on a one-to-one correspondence between the register transfer level code and the register pairs in the gate level netlist;

[0007] Training the circuit encoder through a first self-supervised pre-training task and a second self-supervised pre-training task to generate an embedding vector of the register transfer level code and an embedding vector of the gate level netlist aligned across stages in a shared latent space;

[0008] Wherein, the gate-level netlist is obtained by logic synthesis of the register transfer-level code;

[0009] The first self-supervised pre-training task includes comparing embedding similarities and embedding differences between sub-circuits with the same or different learning functions, and the second self-supervised pre-training task includes randomly masking features of some nodes in the graph and learning to restore features of some randomly masked nodes;

[0010] The embedding vectors include node-level embedding vectors and subcircuit-level embedding vectors.

[0011] A second aspect of an embodiment of the present application provides an application method of a circuit encoder, wherein the circuit encoder is trained based on the training method provided by the first aspect, and the application method includes:

[0012] At least one of a zero-shot reasoning task, a few-shot reasoning task, and a side-loading private data task is performed based on the trained circuit encoder.

[0013] The third aspect of an embodiment of the present application provides a terminal device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the training method provided in the first aspect or the application method provided in the second aspect when executing the computer program.

[0014] The fourth aspect of an embodiment of the present application provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the steps of the training method provided in the first aspect or the application method provided in the second aspect.

[0015] The first aspect of the embodiment of the present application provides a training method for a circuit encoder, which realizes preprocessing of circuit data by converting register transfer level code and gate-level netlist into graphs respectively, extracting features of nodes and edges in the graphs, and extracting subcircuits of each register pair in the register transfer level code and the gate-level netlist based on a one-to-one correspondence between register pairs in the register transfer level code and the gate-level netlist, thereby ensuring that the subcircuits of registers in the register transfer level code and the subcircuits of registers in the corresponding gate-level netlist are functionally equivalent; and by a first self-supervised pre-training task (including but not limited to: comparing and learning the embedding similarities and embedding differences between subcircuits with the same or different functions) and a second self-supervised pre-training task (including but not limited to: randomly masking the features of some nodes in the graph, and learning to restore the features of some nodes that are randomly masked). The circuit encoder is trained to generate embedding vectors of register transfer level code and gate-level netlist that are aligned across stages in a shared latent space, so that the embedding vectors include node-level embedding vectors and sub-circuit-level embedding vectors. The circuit embedding vectors can be aligned in the early register transfer level code and gate-level netlist design stages, ensuring that cross-stage circuit information can be learned in the preset shared latent space, improving the design quality prediction accuracy in the early design stage, achieving consistency and efficiency across stages, and being conducive to improving the functional reasoning capability in the later design stage. It also supports multi-granularity embedding vectors at the node level and sub-circuit level, and can be further aggregated for circuit-level prediction, enhancing the flexibility and adaptability of the circuit encoder, being suitable for EDA tasks of different granularities, and improving the prediction accuracy of downstream tasks.

[0016] The application method of the circuit encoder provided in the second aspect of the embodiment of the present application performs downstream application tasks such as zero-sample reasoning, few-sample reasoning and side-loading of private data through the circuit encoder obtained by training based on the training method provided in the first aspect. When performing zero-sample reasoning or few-sample reasoning tasks, it is possible to perform zero-sample reasoning or few-sample reasoning by retrieving similar circuits, thereby reducing the dependence on a large amount of labeled data, thereby providing high-precision zero-sample reasoning or few-sample reasoning results without additional model training steps, and at the same time, by fine-tuning a small amount of labeled data, it is possible to further improve the prediction accuracy; when performing the side-loading private data task, the private circuit data can be directly side-loaded into the known circuit pool (that is, the circuit data related to the register transfer level code and the gate-level netlist in the first aspect) for retrieval, without the need to pre-train the circuit encoder in the application task execution stage, thereby improving the retrieval efficiency, and on the premise of protecting data privacy, improving the reasoning ability and prediction accuracy of the model, and is suitable for the design process in the EDA design field (for example, integrated circuit (IC), very large-scale integrated circuit (VLSI) and other design processes).

[0017] It can be understood that the beneficial effects of the third and fourth aspects mentioned above can be found in the relevant descriptions of the first and second aspects mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 is a flow chart of a training method for a circuit encoder provided in an embodiment of the present application;

[0020] Figure 2 is a flow chart of a circuit encoder training method provided by another embodiment of the present application;

[0021] Figure 3 is a flow chart of a circuit encoder training method provided by another embodiment of the present application;

[0022] Figure 4 is a flow chart of a circuit encoder training method provided by another embodiment of the present application;

[0023] Figure 5is a flow chart of an application method of a circuit encoder provided by an embodiment of the present application;

[0024] Figure 6 is a schematic diagram of the structure of a circuit encoding device provided in an embodiment of the present application;

[0025] Figure 7 is a structural diagram of a circuit encoding device provided by another embodiment of the present application;

[0026] Figure 8 It is a structural diagram of a terminal device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0027] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0028] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0029] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0030] As used in the specification and appended claims of this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.

[0031] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0032] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0033] The training method and application method of the circuit encoder provided in the embodiment of the present application can be applied to robots, tablet computers, wearable devices, vehicle-mounted devices, augmented reality (AR) / virtual reality (VR) devices, laptops, personal computers (PC), netbooks, personal digital assistants (PDA), industrial computers, servers and other terminal devices, and the terminal devices are executed by running corresponding computer programs through processors during human-computer interaction with users or machine-computer interaction with other devices to respond to user operations or instructions or data sent by other devices. In the embodiment of the present application, there is no restriction on the specific type of terminal devices.

[0034] like Figure 1 As shown, the circuit encoder training method provided in the embodiment of the present application includes the following steps S101 to S104:

[0035] Step S101, converting the register transfer level code into a graph, and extracting the features of the nodes and the features of the edges in the graph corresponding to the register transfer level code, and then proceeding to step S103.

[0036] In applications, Register-Transfer Level (RTL) is a way to describe the function of digital circuits, which focuses on describing how data moves between registers and how the data is processed. RTL description is above the gate level and below the behavioral level. In RTL design, designers focus on how signals are transferred from one register to another and how they are processed by combinational logic.

[0037] In applications, RTL design uses hardware description language (HDL) to describe the behavior of digital and analog circuits. HDL code is usually used to describe the function, internal connection, timing and other characteristics of the circuit, and can be converted into actual hardware implementation by synthesis tools. Several HDLs that can be used in the embodiments of the present application include but are not limited to: VHDL (VHSIC Hardware Description Language), Verilog HDL, Chisel, SpinalHDL, etc. For any other HDL except Verilog HDL, it can be first converted to Verilog HDL using open source tools (for example, Yosys), and then the Verilog code can be parsed into an abstract syntax tree (AST) using tools such as Verilator and Icarus Verilog. For Verilog HDL, the Verilog code can be directly parsed into AST using tools such as Verilator, Icarus Verilog, Py Verilog, etc.

[0038] In applications, each node in AST represents a logical unit (e.g., register, logical operator, arithmetic operator, etc.), and each edge represents the direction of data flow from one node to another. The conversion of RTL code to graph is the process of mapping the information of nodes and edges in AST to the graph. The characteristics of the nodes in the graph corresponding to AST include at least one of the operation type and bit width, and the characteristics of the edges include the operation type of the nodes connected by the edges.

[0039] In the application, a suitable parser can be used to parse the register transfer level code to generate an AST, traverse the AST, extract node and edge information from the AST, build a graph data structure based on the extracted node and edge information, extract the features of each node and edge, and store the graph data structure and the extracted node and edge features in a default or custom storage space (for example, a graph database) to facilitate subsequent analysis or machine learning tasks.

[0040] like Figure 2 As shown, in one embodiment, step S101 includes the following steps S201 to S203:

[0041] Step S201, converting the hardware description language of the register transfer level code into an abstract syntax tree, and proceeding to step S202;

[0042] Step S202, traverse all nodes and all edges in the abstract syntax tree to generate a graph corresponding to the register transfer level code, and proceed to step S203;

[0043] Step S203 , extract the features of the nodes and edges in the graph corresponding to the register transfer level code, and proceed to step S103 .

[0044] In applications, by converting RTL code into a graph and extracting useful node and edge features from it, it provides a basis for further analysis and machine learning tasks.

[0045] Step S102: Convert the gate-level netlist into a graph, and extract the features of the nodes and edges in the graph corresponding to the gate-level netlist, and proceed to step S103.

[0046] In applications, a gate-level netlist is a representation method for describing digital circuits at the gate-level abstraction level. It describes in detail the logic gates in the circuit (e.g., AND gates, NOT gates, OR gates, etc.) and the connections between these gates. The gate-level netlist is generated by a logic synthesis tool from RTL code at a higher level of abstraction. It is a result of the logic synthesis process, in which the registers in the RTL code are synthesized into specific flip-flops and logic gates. A flip-flop can be composed of several logic gates (e.g., a D flip-flop can be composed of a NOT gate and two NAND gates).

[0047] In applications, each trigger or logic gate in a gate-level netlist can be regarded as a node, and the line between two nodes represents the connection relationship of the logic gates, which can be modeled as an edge. The conversion of a gate-level netlist to a graph is the process of mapping the information of nodes and edges in a gate-level netlist to a graph. The characteristics of the nodes in the graph corresponding to the gate-level netlist include at least one of type, fan-in number, fan-out number, driving capability, unit area, output capacitance and resistance, and the characteristics of the edges include at least one of direction, signal propagation delay time and load conditions of subsequent nodes.

[0048] In applications, appropriate tools or scripts can be used to parse gate-level netlist files (usually text files, such as Verilog format) to extract information and connection relationships of logic gates. After parsing the netlist, a graph data structure can be created to represent the digital circuit of the gate-level netlist, extract the features of each node and edge, and store the graph data structure and the extracted node and edge features in a default or custom storage space (e.g., a graph database or graph processing library) to facilitate subsequent analysis or machine learning tasks.

[0049] like Figure 2 As shown, in one embodiment, step S102 includes the following steps S204 to S205:

[0050] Step S204, taking the triggers and logic gates in the gate-level netlist as nodes, and taking the connections between the nodes in the gate-level netlist as edges, generating a graph corresponding to the gate-level netlist, and proceeding to step S205;

[0051] Step S205 , extract the features of the nodes and edges in the graph corresponding to the gate-level netlist, and proceed to step S103 .

[0052] In applications, by converting the gate-level netlist into a graph and extracting useful node and edge features from it, it provides a basis for further analysis and machine learning tasks.

[0053] Step S103 , based on the one-to-one correspondence between the register transfer level code and the register pairs in the gate level netlist, extract the subcircuit of each register pair in the register transfer level code and the gate level netlist from the graph, and proceed to step S104 .

[0054] In applications, in RTL design, registers are defined in a behavioral description manner. For example, in hardware description languages ​​such as Verilog HDL or VHDL, registers are declared as variables, and their value changes are controlled by sequential logic (such as triggers). In gate-level netlist design, registers are specifically implemented as triggers composed of a series of logic gates (such as AND gates and NOT gates). The gate-level netlist is automatically converted from the RTL code by the synthesis tool. During this process, the registers will be synthesized into a specific logic gate circuit structure. An RTL register will be synthesized into a gate-level trigger, so that an RTL register will correspond to a gate-level trigger. However, it should be noted that this correspondence is not an absolute one-to-one correspondence, but can also be one-to-many or many-to-one.

[0055] In the application, for the graph corresponding to the RTL code or gate-level netlist, in the subcircuit extraction process of each register pair, start from the register and traverse the data path in reverse until reaching the register of other drivers. Based on the correspondence between register pairs, all combinatorial logic components traced back are extracted from the graph corresponding to the RTL code and gate-level netlist to form subcircuits, ensuring that they are functionally equivalent, thus achieving the extraction and alignment of subcircuits.

[0056] Step S104: Train the circuit encoder through the first self-supervised pre-training task and the second self-supervised pre-training task to generate an embedding vector of the register transfer level code and an embedding vector of the gate level netlist that are aligned across stages in a shared latent space.

[0057] In the application, the first self-supervised pre-training task (also known as the multi-stage contrastive learning task) includes contrastive learning of the embedding similarities and embedding differences between sub-circuits with the same or different functions. The goal of the first self-supervised pre-training task is to enable the model (also known as the circuit encoder) to distinguish between circuits with the same and different functions through contrastive learning. Within the same design stage (RTL design stage or gate-level netlist design stage), the model should be able to correctly judge that the embeddings of sub-circuits with the same functions are similar, while the embeddings of sub-circuits with different functions have significant differences; between different design stages (for example, from the RTL design stage to the gate-level netlist design stage), the model should also be able to correctly judge that the embeddings of sub-circuits with the same functions are similar, while the embeddings of sub-circuits with different functions across stages have significant differences.

[0058] In one embodiment, the first self-supervised pre-training task specifically includes:

[0059] Compare and learn the embedding similarities and differences between subcircuits in register-transfer-level codes with the same or different functions;

[0060] Compare and learn the embedding similarities and differences between subcircuits in gate-level netlists with the same or different functions;

[0061] Compare and learn the embedding similarities and differences between subcircuits in register transfer level code and subcircuits in gate level netlist with the same functions;

[0062] The embedding similarities and differences between subcircuits in register-transfer-level codes and gate-level netlists with different functions are compared and learned.

[0063] In applications, by performing comparative learning within the same design stage, it can be ensured that the embedding vectors of sub-circuits with the same functions are similar, and the embedding vectors of sub-circuits with different functions are significantly different; by performing comparative learning between different design stages, it can be ensured that the embedding vectors of sub-circuits in RTL code and gate-level netlist with the same functions are similar, and the embedding vectors of sub-circuits with different functions across stages are significantly different.

[0064] In the application, the second self-supervised pre-training task (also known as the Masked Node Recovery task) includes randomly masking the features of some nodes in the graph and learning to recover the features of some nodes that are randomly masked. This is a task similar to the masked language model in the field of natural language processing. In the second self-supervised pre-training task, the model (also known as the circuit encoder) needs to recover the features of the obscured nodes based on the unobstructed parts of the circuit diagram, which helps the model learn the dependencies between nodes in the circuit diagram.

[0065] In one embodiment, the second self-supervised pre-training task specifically includes:

[0066] The features of some nodes in the graph corresponding to the random mask register transfer level code, and learn to recover the features of some nodes that are randomly masked;

[0067] The features of some nodes in the graph corresponding to the randomly masked gate-level netlist are learned, and the features of some nodes that are randomly masked are recovered.

[0068] In the application, the circuit encoder is trained through the first self-supervised pre-training task and the second self-supervised pre-training task, and the embedded vectors of the register transfer level code and the gate level netlist aligned across stages are generated in the shared latent space, so that the embedded vectors include the node level embedded vectors and the sub-circuit level embedded vectors, and the circuit embedded vectors can be aligned in the early register transfer level code and gate level netlist design stages, ensuring that the cross-stage circuit information can be learned in the preset shared latent space, improving the design quality prediction accuracy in the early design stage, achieving consistency and efficiency across stages, and being conducive to improving the functional reasoning ability in the later design stage, and also supporting multi-granularity embedded vectors at the node level and sub-circuit level, and can be further aggregated for circuit-level prediction, enhancing the flexibility and adaptability of the circuit encoder, and being suitable for EDA tasks of different granularities, and improving the prediction accuracy of downstream tasks. Shared latent space refers to the situation in machine learning and deep learning where two or more models or model components share the same latent space. The latent space refers to a low-dimensional space to which the high-dimensional input data is mapped by the encoder. This space usually contains the key features and structural information of the input data. Each node or vector in the latent space can be regarded as an abstract data representation corresponding to the original input data. Sharing the latent space means that different models or parts of the model can access the same data representation.

[0069] like Figure 3 As shown, in one embodiment, step S104 includes the following steps S301 to S305:

[0070] Step S301, encode the graph corresponding to the register transfer level code, generate an embedding vector of the register transfer level code, and proceed to steps S303 and S304;

[0071] Step S302, encode the graph corresponding to the gate-level netlist to generate an embedding vector of the gate-level netlist, and proceed to steps S303 and S304;

[0072] Step S303: training the circuit encoder through a first self-supervised pre-training task to generate an embedding vector of the register transfer level code and an embedding vector of the gate level netlist aligned across stages in a shared latent space;

[0073] Step S304: training the circuit encoder through a second self-supervised pre-training task.

[0074] In applications, at the RTL stage, a graph transformer model (other graph neural networks can also be used as backbone networks) can be used to encode the RTL circuit diagram (that is, the graph corresponding to the RTL). The graph transformer model is a deep learning model that can process non-Euclidean data, such as graph structured data. The graph transformer model can convert the RTL circuit diagram into a set of node embedding vectors and cone embedding vectors. The node embedding vector represents the characteristics of a single node, while the cone embedding vector represents the characteristics of the local area surrounding a node. The characteristics of the nodes in the graph corresponding to the register transfer level code include the operation type and bit width, and the characteristics of the edges include the operation type of the nodes connected by the edges.

[0075] like Figure 4 As shown, in one embodiment, the circuit encoder includes a graph converter model, and step S301 includes the following steps S401 to S402:

[0076] Step S401, performing center encoding, space encoding and edge encoding on the graph corresponding to the register transfer level code based on the graph transformer model, generating a node-level embedding vector of the register transfer level code, and proceeding to step S402;

[0077] Step S402 , based on the preset global nodes and each node in the graph corresponding to the register transfer level code, edges are formed to generate a subcircuit level embedding vector of the register transfer level code, and then proceed to steps S303 and S304 .

[0078] In the application, the center encoding uses the fan-in and fan-out of the node in the graph corresponding to the register transfer level code as the degree of the node. The space encoding is used to calculate the shortest path distance between all nodes in the graph corresponding to the register transfer level code. The edge encoding is implemented based on the characteristics of the edges in the graph corresponding to the register transfer level code.

[0079] In applications, at the gate-level netlist stage, a Graph Neural Network (GNN) model (other graph neural networks can also be used as the backbone network) can be used to encode the gate-level netlist circuit diagram (that is, the graph corresponding to the gate-level netlist). GNN is also a deep learning model suitable for graph-structured data, which can convert the gate-level netlist circuit diagram into a set of node embedding vectors and pyramid embedding vectors. The node embedding vector represents the characteristics of a single node, while the pyramid embedding vector represents the characteristics of the local area surrounding a node. The characteristics of the nodes in the graph corresponding to the gate-level netlist include type, fan-in number, fan-out number, drive capability, unit area, output capacitance and resistance.

[0080] like Figure 4 As shown, in one embodiment, the circuit encoder includes a GNN model, and step S302 includes the following steps S403 to S404:

[0081] Step S403, aggregating information of nodes in the graph corresponding to the gate-level netlist based on the message passing mechanism, generating a node-level embedding vector of the gate-level netlist, and proceeding to step S404;

[0082] Step S404: average pooling is performed on the node-level embedding vectors of the gate-level netlist, and the node-level embedding vectors of the gate-level netlist are aggregated into sub-circuit-level embedding vectors, and the process proceeds to steps S303 and S304.

[0083] In an application, information about nodes in a graph corresponding to a gate-level netlist includes at least one of node characteristics, edge characteristics, node status, adjacent node status, and node location information.

[0084] like Figure 5 As shown, the application method of the circuit encoder provided in the embodiment of the present application, based on the above-mentioned training method, also includes step S105, performing at least one of a zero-sample reasoning task, a few-sample reasoning task and a side-loading private data task based on the trained circuit encoder.

[0085] In the application, when performing zero-shot inference, based on the trained circuit encoder, using the pre-trained circuit embedding vector, by retrieving similar circuits, the retrieved circuit properties are directly used for inference, thereby providing high-precision zero-shot inference results without additional model training steps. When performing few-shot inference, fine-tuning lightweight models for downstream tasks based on the trained circuit encoder and a small amount of labeled data can improve prediction accuracy. When performing side-loading private data, private circuit data is directly side-loaded into the known circuit pool for retrieval, which can enhance the model's reasoning ability and prediction accuracy while ensuring data privacy.

[0086] In application, the above application method is applicable to the design process in the EDA design field (for example, IC, VLSI and other design processes). The specific application scenario examples are as follows:

[0087] 1. Design quality prediction of RTL code in circuit design

[0088] Based on the RTL code in the circuit design, the circuit designer can use the above application method to directly predict the circuit timing, power consumption, area, etc., without the need for time-consuming logic synthesis process, which can effectively improve the prediction efficiency and accuracy;

[0089] Training data: The timing, power consumption, area, etc. of the RTL code (open source data set) in the circuit design after logic synthesis are used as training labels. When performing few-sample reasoning, these training labels are fine-tuned to improve prediction accuracy;

[0090] Output: The timing of the RTL code in the design circuit (for example, the timing margin (slack) of each register, the total negative margin (total negative slack) and the worst negative slack (worst negative slack), total power consumption, total area and other predicted values.

[0091] 2. Functional reasoning of the netlist after circuit logic synthesis

[0092] 1) When identifying the state register at the gate-level netlist stage, the functions implemented by the gate-level netlist are inferred based on the gate-level netlist after logic synthesis, and the control logic registers and data path registers in the gate-level netlist are distinguished, which can be widely used in hardware security, circuit function verification and other fields;

[0093] Training data: The gate-level netlist after logic synthesis in the circuit design (from the same source as above) and the register type (control logic or data path) before logic synthesis are used as training labels. When performing few-shot reasoning, these training labels are fine-tuned to improve prediction accuracy.

[0094] Output data: the register type (control logic or data path) of the gate-level netlist in the designed circuit;

[0095] 2) When predicting the probability of logic gate flipping at the gate-level netlist stage, the signal flipping rate of the logic gate in the gate-level netlist is inferred based on the gate-level netlist after logic synthesis. The flipping rate can be further used for circuit function verification and power consumption prediction;

[0096] Training data: The signal flip rate (obtained through simulation) of each logic gate in the gate-level netlist after logic synthesis in the circuit design (source as above) is used as the training label. When performing few-shot reasoning, these training labels are fine-tuned to improve prediction accuracy.

[0097] Output data: The flip rate of each logic gate in the gate-level netlist of the designed circuit.

[0098] The embodiments of the present application provide an efficient, universal and accurate circuit encoder by combining learning based on self-supervised training tasks, cross-stage alignment, multi-granularity embedding, retrieval-enhanced reasoning and side-loading enhancement technology. The circuit encoder can significantly improve the processing capabilities of various types of machine learning-based EDA tasks and greatly simplify the development process of these tasks.

[0099] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0100] The present application also provides a circuit encoding device for executing the steps in the above training method embodiment. The circuit encoding device may be a virtual appliance (e.g., a circuit encoder) in a terminal device, which is run by a processor of the terminal device, or may be the terminal device itself. Figure 6 As shown, the circuit encoding device 100 provided in the embodiment of the present application includes:

[0101] The register transfer level graph conversion module 101 is used to convert the register transfer level code into a graph, and extract the features of the nodes and edges in the graph corresponding to the register transfer level code, and enter the sub-circuit extraction module 103;

[0102] A gate-level graph conversion module 102, used to convert a gate-level netlist into a graph and extract features of nodes and edges in the graph corresponding to the gate-level netlist, and a subcircuit extraction module 103;

[0103] A subcircuit extraction module 103 is used to extract the subcircuit of each register pair in the register transfer level code and the gate level netlist from the graph based on the one-to-one correspondence between the register pairs in the register transfer level code and the gate level netlist, and enter the self-supervised pre-training cross-stage alignment module 104;

[0104] The self-supervised pre-training cross-stage alignment module 104 is used to train the circuit encoder through a first self-supervised pre-training task and a second self-supervised pre-training task to generate an embedding vector of the register transfer level code and an embedding vector of the gate level netlist that are aligned across stages in a shared latent space.

[0105] In one embodiment, the circuit encoding device 100 is also used to execute the steps in the above-mentioned application method embodiment. Figure 7 As shown, the circuit encoding device 100 further includes:

[0106] The application module 105 is used to perform at least one of a zero-sample reasoning task, a few-sample reasoning task, and a side-loading private data task based on the trained circuit encoder.

[0107] In application, each module in the circuit encoding device may be a software program module, or may be implemented by different logic circuits integrated in a processor, or may be implemented by multiple distributed processors.

[0108] Figure 8 The present application also provides a terminal device 200, including: at least one processor 201 ( Figure 8 Only one processor is shown in the figure), a memory 202, and a computer program 203 stored in the memory 202 and executable on at least one processor 201, wherein the processor 201 implements the steps of any of the above method embodiments when executing the computer program 203.

[0109] In the application, the terminal device may include, but is not limited to, a processor and a memory. Those skilled in the art will understand that Figure 8 It is only an example of a terminal device and does not constitute a limitation on the terminal device. It may include more or fewer components than shown in the figure, or a combination of certain components, or different components. For example, it may also include input and output devices, network access devices, etc.

[0110] In applications, the processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc.

[0111] In applications, the memory may be an internal storage unit of a terminal device in some embodiments, such as a hard disk or memory of the terminal device. In other embodiments, the memory may also be an external storage device of the terminal device, such as a plug-in hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (SecureDigital, SD) card, a flash card (Flash Card), etc. equipped on the terminal device. Further, the memory may also include both an internal storage unit of the terminal device and an external storage device. The memory is used to store an operating system, an application program, a boot loader (BootLoader), data, and other programs, such as program codes of a computer program. The memory may also be used to temporarily store data that has been output or is to be output.

[0112] It should be noted that the information interaction, execution process, etc. between the above-mentioned devices / modules are based on the same concept as the method embodiment of the present application. Their specific functions and technical effects can be found in the method embodiment part and will not be repeated here.

[0113] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. The functional modules in the embodiment can be integrated into a processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The above-mentioned integrated modules can be implemented in the form of hardware or in the form of software functional modules. In addition, the specific names of the functional modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the modules in the above-mentioned device can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0114] An embodiment of the present application also provides a network device, which includes: at least one processor, a memory, and a computer program stored in the memory and executable on at least one processor, and the processor implements the steps in the above-mentioned method embodiments when executing the computer program.

[0115] The embodiment of the present application further provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments can be implemented.

[0116] An embodiment of the present application provides a computer program product. When the computer program product runs on a terminal device, the terminal device can implement the steps in the above-mentioned method embodiments when executing the computer program product.

[0117] If the integrated module is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, which can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a computer-readable storage medium. When the computer program is executed by the processor, the steps of the above-mentioned various method embodiments can be implemented. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may at least include: any entity or device that can carry the computer program code to the device / terminal device, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electric carrier signal, a telecommunication signal, and a software distribution medium. For example, a USB flash drive, a mobile hard disk, a magnetic disk or an optical disk. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electric carrier signals and telecommunication signals.

[0118] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0119] Those of ordinary skill in the art will appreciate that the modules and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0120] In the embodiments provided in the present application, it should be understood that the disclosed devices / equipment and methods can be implemented in other ways. For example, the device / equipment embodiments described above are only schematic, for example, the division of modules is only a logical function division, and there may be other division methods in actual implementation, such as multiple modules or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0121] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0122] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A circuit encoder training method, characterized in that: The training method comprises: Converting register transfer level code and gate level netlist into graphs respectively, and extracting features of nodes and edges in the graphs; extracting from the graph a subcircuit of each register pair in the register transfer level code and the gate level netlist based on a one-to-one correspondence between the register transfer level code and the register pairs in the gate level netlist; Training the circuit encoder through a first self-supervised pre-training task and a second self-supervised pre-training task to generate an embedding vector of the register transfer level code and an embedding vector of the gate level netlist aligned across stages in a shared latent space; Wherein, the gate-level netlist is obtained by logic synthesis of the register transfer-level code; The first self-supervised pre-training task includes comparing embedding similarities and embedding differences between sub-circuits with the same or different learning functions, and the second self-supervised pre-training task includes randomly masking features of some nodes in the graph and learning to restore features of some randomly masked nodes; The embedding vectors include node-level embedding vectors and subcircuit-level embedding vectors.

2. The training method according to claim 1, characterized in that: The register transfer level code and the gate level netlist are respectively converted into graphs, and the features of the nodes and the features of the edges in the graphs are extracted, including: Converting the hardware description language of register transfer level code into an abstract syntax tree; Traversing all nodes and all edges in the abstract syntax tree to generate a graph corresponding to the register transfer level code; Extracting features of nodes and edges in a graph corresponding to the register transfer level code; Using triggers and logic gates in a gate-level netlist as nodes and using connections between nodes in the gate-level netlist as edges to generate a graph corresponding to the gate-level netlist; Extracting features of nodes and edges in a graph corresponding to the gate-level netlist; The nodes in the abstract syntax tree are at least used to represent registers, the edges in the abstract syntax tree are used to represent the direction of data flow, and the edges in the gate-level netlist are used to represent the connection relationship of logic gates.

3. The training method according to claim 2, characterized in that: The characteristics of the nodes in the graph corresponding to the register transfer level code include at least one of an operation type and a bit width, and the characteristics of the edges in the graph corresponding to the register transfer level code include the operation types of the nodes connected by the edges; The characteristics of the nodes in the graph corresponding to the gate-level netlist include at least one of type, fan-in number, fan-out number, driving capability, unit area, output capacitance and resistance, and the characteristics of the edges in the graph corresponding to the gate-level netlist include at least one of direction, signal propagation delay time and load conditions of subsequent nodes.

4. The training method according to claim 1, characterized in that: The circuit encoder is trained by a self-supervised pre-training task to generate an embedding vector of the register transfer level code and an embedding vector of the gate level netlist aligned across stages in a shared latent space, including: Encoding a graph corresponding to the register transfer level code to generate an embedding vector of the register transfer level code; Encoding a graph corresponding to the gate-level netlist to generate an embedding vector of the gate-level netlist; Training the circuit encoder through a first self-supervised pre-training task to generate an embedding vector of the register transfer level code and an embedding vector of the gate-level netlist aligned across stages in a shared latent space; training the circuit encoder via a second self-supervised pre-training task; The characteristics of the nodes in the graph corresponding to the register transfer level code include operation type and bit width; The characteristics of the nodes in the graph corresponding to the gate-level netlist include type, fan-in number, fan-out number, driving capability, unit area, output capacitance and resistance.

5. The training method according to claim 4, characterized in that: The circuit encoder includes a graph transformer model; Encoding a graph corresponding to the register transfer level code to generate an embedding vector of the register transfer level code includes: Based on the graph transformer model, center encoding, space encoding and edge encoding are performed on the graph corresponding to the register transfer level code to generate a node-level embedding vector of the register transfer level code; Based on the preset global nodes respectively forming edges with each node in the graph corresponding to the register transfer level code, generating a sub-circuit level embedding vector of the register transfer level code; The central encoding uses the fan-in number and the fan-out number of the node in the graph corresponding to the register transfer level code as the degree of the node; The spatial encoding is used to calculate the shortest path distance between all nodes in the graph corresponding to the register transfer level code; The edge encoding is implemented based on the features of the edges in the graph corresponding to the register transfer level code.

6. The training method according to claim 4, characterized in that: The circuit encoder includes a graph neural network model; Encoding a graph corresponding to the gate-level netlist based on the graph neural network model to generate an embedding vector of the gate-level netlist includes: Aggregating information of nodes in the graph corresponding to the gate-level netlist based on a message passing mechanism to generate a node-level embedding vector of the gate-level netlist; Performing average pooling on the node-level embedding vectors of the gate-level netlist, and aggregating the node-level embedding vectors of the gate-level netlist into sub-circuit-level embedding vectors; The information of the nodes in the graph corresponding to the gate-level netlist includes at least one of the characteristics of the nodes, the characteristics of the edges, the status of the nodes, the status of the adjacent nodes and the location information of the nodes.

7. The training method according to any one of claims 4 to 6, characterized in that: The first self-supervised pre-training task specifically includes: Comparatively learning the embedding similarities and embedding differences between sub-circuits in the register transfer level code with the same or different learning functions; Comparative learning of embedding similarities and embedding differences between subcircuits in the gate-level netlist with the same or different functions; Comparatively learning the embedding similarities and embedding differences between the subcircuits in the register transfer level code and the subcircuits in the gate level netlist with the same functions; Comparatively learning the embedding similarities and embedding differences between the subcircuits in the register transfer level code and the subcircuits in the gate level netlist with different functions; The second self-supervised pre-training task specifically includes: Randomly masking the features of some nodes in the graph corresponding to the register transfer level code, and learning to restore the features of some nodes that are randomly masked; The features of some nodes in the graph corresponding to the gate-level netlist are randomly masked, and the features of some nodes that are randomly masked are restored through learning.

8. An application method of a circuit encoder, characterized in that: The circuit encoder is trained based on the training method according to any one of claims 1 to 7, and the application method comprises: At least one of a zero-shot reasoning task, a few-shot reasoning task, and a side-loading private data task is performed based on the trained circuit encoder.

9. A terminal device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the training method according to any one of claims 1 to 7 or the application method according to claim 8 are implemented.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the training method according to any one of claims 1 to 7 or the application method according to claim 8 are implemented.

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