Information interaction method and device

Abstract

The embodiment of the invention discloses an information interaction method and device. According to the embodiment of the invention, after a congestion hotspot analysis instruction is received, congestion hotspot analysis is carried out on a to-be-tested gate-level netlist to determine at least one combinational logic congestion hotspot, and a to-be-modified code statement is determined in a register transfer-level code according to the combinational logic congestion hotspot; and modifying each to-be-modified code statement into a target code statement, and regenerating a target gate-level netlist according to the modified register transfer-level code. Wherein the to-be-modified code statement only supports to be converted into a combinational logic structure in the logic synthesis process, and the target code statement supports to be converted into a multiplexer structure in the logic synthesis process. Therefore, the embodiment of the invention can support a user to analyze and solve the wiring congestion problem in the logic synthesis process, so that the chip design efficiency is improved, and the negative effects of the wiring congestion problem solving process on the power consumption, the performance and the area of the formed chip are reduced.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and more particularly, to an information interaction method and apparatus. Background Art

[0002] With the continuous progress of semiconductor process nodes, chip design has become increasingly complex, and the GRC (Global Route Congestion) problem has gradually become a significant challenge in chip physical implementation. Especially when using advanced process nodes and cache logic containing a large number of crossbar structures, the GRC problem is particularly prominent. Currently, the traditional integrated circuit design process usually discovers and solves the GRC problem in the routing stage of physical implementation, that is, in the later stage of integrated circuit design. However, the means to solve the GRC problem in the routing stage are often limited and require a long time period, and it will also have a negative impact on the power consumption, performance, and area of the formed chip. Summary of the Invention

[0003] In view of this, embodiments of the present invention provide an information interaction method and apparatus to support users in analyzing and solving the wiring congestion problem during logic synthesis, thereby improving chip design efficiency and reducing the negative impact on the power consumption, performance, and area of the formed chip during the process of solving the wiring congestion problem.

[0004] In a first aspect, an embodiment of the present invention aims to provide an information interaction method, the method comprising:

[0005] Receiving a congestion hot spot analysis instruction;

[0006] Performing congestion hot spot analysis on a to-be-tested gate-level netlist to determine at least one combinational logic congestion hot spot, where the combinational logic congestion hot spot is a congestion hot spot generated due to a combinational logic structure;

[0007] Determining a to-be-modified code statement in the register transfer level code according to the combinational logic congestion hot spot, where the to-be-modified code statement only supports being converted into a combinational logic structure during logic synthesis;

[0008] For each of the to-be-modified code statements, modifying the to-be-modified code statement into a target code statement, where the target code statement supports being converted into a multiplexer structure during logic synthesis;

[0009] Regenerating a target gate-level netlist according to the modified register transfer level code.

[0010] In a second aspect, an embodiment of the present invention aims to provide an information interaction apparatus, the apparatus comprising:

[0011] A receiving unit, configured to receive a congestion hot spot analysis instruction;

[0012] A congestion hot spot determination unit, configured to perform congestion hot spot analysis on a to-be-tested gate-level netlist to determine at least one combinational logic congestion hot spot, where the combinational logic congestion hot spot is a congestion hot spot generated due to a combinational logic structure;

[0013] A to-be-modified code statement determination unit, configured to determine a to-be-modified code statement in a register transfer level code according to the combinational logic congestion hot spot, where the to-be-modified code statement only supports being converted into a combinational logic structure during logic synthesis;

[0014] A code statement modification unit, configured to modify each of the to-be-modified code statements into a target code statement, where the target code statement supports being converted into a multiplexer structure during logic synthesis;

[0015] A gate-level netlist generation unit, configured to regenerate a target gate-level netlist according to the modified register transfer level code.

[0016] In a third aspect, an embodiment of the present invention aims to provide a computer-readable storage medium, on which computer program instructions are stored, and when the computer program instructions are executed by a processor, the method described in the first aspect is implemented.

[0017] In a fourth aspect, an embodiment of the present invention aims to provide an electronic device, where the device includes:

[0018] A memory, configured to store one or more computer program instructions;

[0019] A processor, where the one or more computer program instructions are executed by the processor to implement the method described in the first aspect.

[0020] In a fifth aspect, an embodiment of the present invention aims to provide a computer program product, and when the computer program product runs on a computer, the computer is caused to execute the method described in the first aspect.

[0021] After receiving the congestion hotspot analysis instruction, the embodiments of the present invention perform congestion hotspot analysis on the gate-level netlist to be tested to determine at least one combinational logic congestion hotspot, determine the code statements to be modified in the register transfer level code according to the combinational logic congestion hotspot, and then modify each code statement to be modified into a target code statement, and then regenerate the target gate-level netlist according to the modified register transfer level code. Among them, the code statements to be modified only support being converted into combinational logic structures during the logic synthesis process, and the target code statements support being converted into multiplexer structures during the logic synthesis process. Thus, the embodiments of the present invention can support users to analyze and solve the routing congestion problem during the logic synthesis process, thereby improving the chip design efficiency and reducing the negative impacts on the power consumption, performance, and area of the formed chip during the process of solving the routing congestion problem. Description of the Drawings

[0022] Through the following description of the embodiments of the present invention with reference to the drawings, the above and other objects, features, and advantages of the present invention will become clearer. In the drawings:

[0023] Figure 1 It is a flowchart of the information interaction method according to the embodiment of the present invention;

[0024] Figure 2 It is a flowchart of the method for generating the gate-level netlist to be tested according to the embodiment of the present invention;

[0025] Figure 3 It is a flowchart of the method for determining the combinational logic congestion hotspot according to the embodiment of the present invention;

[0026] Figure 4 It is a flowchart of the congestion hotspot analysis method according to the embodiment of the present invention;

[0027] Figure 5 It is a flowchart of the method for determining the code statements to be modified according to the embodiment of the present invention;

[0028] Figure 6 It is a flowchart of the code statement modification method according to the embodiment of the present invention;

[0029] Figure 7 It is a flowchart of the method for generating the target gate-level netlist according to the embodiment of the present invention;

[0030] Figure 8 It is a flowchart of the evaluation data display method according to the embodiment of the present invention;

[0031] Figure 9 It is a schematic diagram of the information interaction device according to the embodiment of the present invention;

[0032] Figure 10 It is a schematic diagram of the electronic device according to the embodiment of the present invention. Detailed Embodiments

[0033] The present application will be described based on embodiments, but the present application is not limited to these embodiments. In the following detailed description of the present application, some specific details are described in detail. Those skilled in the art can fully understand the present application without the description of these details. In order to avoid obscuring the essence of the present application, well-known methods, processes, procedures, components, and circuits are not described in detail.

[0034] In addition, those of ordinary skill in the art should understand that the drawings provided herein are for illustrative purposes only, and the drawings are not necessarily drawn to scale.

[0035] Unless the context clearly requires otherwise, words such as "including" and "comprising" in the entire application document should be interpreted as having an inclusive meaning rather than an exclusive or exhaustive meaning; that is, the meaning of "including but not limited to".

[0036] In the description of the present application, it should be understood that terms such as "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0037] For the solutions described in this specification and the embodiments, if they involve the processing of personal information, they will be processed on the premise of having a legal basis (such as obtaining the consent of the personal information subject, or being necessary for performing a contract, etc.), and will only be processed within the specified or agreed scope. If the user refuses to process personal information other than the necessary information required for the basic functions, it will not affect the user's use of the basic functions.

[0038] Figure 1 It is a flowchart of the information interaction method according to the embodiments of the present invention. It is hoped to illustrate that Figure 1The execution subject of the information interaction method shown can be a general data processing device. In this embodiment, by executing the information interaction method, the data processing device can interact with the user to support the user in analyzing and solving the routing congestion problem during the logic synthesis process, thereby improving the chip design efficiency and reducing the negative impact on the power consumption, performance, and area of the formed chip caused by the process of solving the routing congestion problem. Optionally, the data processing device can be a personal computer (e.g., a desktop computer, a laptop computer, or a desktop computer, etc.), or a server (the server can be a single computer, or a cluster composed of multiple computers, or a cloud server that can elastically adjust computing resources through cloud technology), etc. This application does not limit this. It should be understood that when the data processing device is a personal computer, the data processing device can directly implement information interaction with the user through externally connected input and output devices. When the data processing device is a server, the data processing device can indirectly implement information interaction with the user through the terminal device held by the user. As Figure 1 shown, the information interaction method may specifically include the following steps:

[0039] Step S100, receive a congestion hotspot analysis instruction.

[0040] Specifically, the data processing device can receive a congestion hotspot analysis instruction. Among them, the congestion hotspot analysis instruction can be triggered by the user, and it can be used to instruct the data processing device to provide a congestion hotspot analysis service for the to-be-tested gate-level netlist. Here, the to-be-tested gate-level netlist can refer to the gate-level netlist generated after logically synthesizing the current latest register-transfer level (RTL) code. It should be noted that in this embodiment, since the data processing device will support the user to modify the register-transfer level code according to the congestion hotspot analysis result, the current latest register-transfer level code can be either the register-transfer level code first input by the user or the register-transfer level code most recently modified by the user. This application does not limit this.

[0041] Optionally, for the register-transfer level code first input, before receiving the congestion hotspot analysis instruction, the data processing device can also first provide a logic synthesis service to generate the to-be-tested gate-level netlist for the first time.

[0042] Figure 2 This is a flowchart of the method for generating a to-be-tested gate-level netlist according to an embodiment of the present invention. It should be understood that by executing the method for generating a to-be-tested gate-level netlist as Figure 2 shown, the data processing device can generate a to-be-tested gate-level netlist. As Figure 2As shown, the method for generating the gate-level netlist to be tested may specifically include the following steps:

[0043] Step S110: Receive the register transfer level code.

[0044] Specifically, the data processing device may receive the register transfer level code. Optionally, the register transfer level code may be directly written by the user at the data processing device, or may be written by the user at other devices and then imported into the data processing device. This application does not limit this.

[0045] Step S120: Perform logic synthesis on the register transfer level code to determine the gate-level netlist to be tested corresponding to the register transfer level code.

[0046] Specifically, after receiving the register transfer level code, the data processing device may perform logic synthesis on the register transfer level code to determine the gate-level netlist to be tested corresponding to the register transfer level code.

[0047] It should be noted that the register transfer level code can be understood as a high-level abstraction description of the process of data transfer and conversion between registers written in a hardware description language. Optionally, the register transfer level code may be written based on Verilog, VHDL (Very High Speed Integrated Circuit Hardware Description Language), SystemVerilog, or any other type of hardware description language. This application does not limit this. Logic synthesis can be understood as the process of converting the high-level register transfer level code into a low-level gate-level representation. Optionally, in step S120, the implementation of the logic synthesis process can be achieved by the data processing device by calling the functions in the electronic design automation software. This application does not limit this. The gate-level netlist can be understood as the output result obtained after performing logic synthesis on the register transfer level code. All the logic units required to implement the register transfer level code and the connection relationships between the logic units are listed in detail in this gate-level netlist.

[0048] Step S200: Perform congestion hot spot analysis on the gate-level netlist to be tested to determine at least one combinational logic congestion hot spot.

[0049] Specifically, after receiving the congestion hot spot analysis instruction, the data processing device may perform congestion hot spot analysis on the gate-level netlist to be tested to determine at least one combinational logic congestion hot spot. Among them, the combinational logic congestion hot spot may refer to the congestion hot spot generated due to the combinational logic structure.

[0050] It should be noted that the register transfer level code usually contains selection code statements for expressing selection or assignment logic, such as if statements, case statements, and assign statements. These selection code statements will be converted into multiplexer structures or combinational logic structures during the logic synthesis process. Among them, both the multiplexer structure and the combinational logic structure are hardware structures. Compared with the multiplexer structure, the combinational logic structure is usually composed of multiple basic logic units (such as AND gates, OR gates, NOT gates, etc.) and thus has the advantages of small area and fast speed. However, the combinational logic structure often also has a relatively large number of pins, which is the main reason for the occurrence of wiring congestion problems. In this embodiment, in order to solve the wiring congestion problem, the data processing device can first find the combinational logic congestion hotspots in the to-be-tested gate-level netlist.

[0051] Optionally, in step S200, the data processing device can determine the combinational logic congestion hotspots among multiple candidate congestion hotspots according to the user's instruction.

[0052] Figure 3 It is a flowchart of the method for determining combinational logic congestion hotspots according to an embodiment of the present invention. It should be understood that by executing the method for determining combinational logic congestion hotspots as Figure 3 shown, the data processing device can determine the combinational logic congestion hotspots among multiple candidate congestion hotspots according to the user's instruction, that is, implement the above step S200. As Figure 3 shown, the method for determining combinational logic congestion hotspots may specifically include the following steps:

[0053] Step S210: Perform congestion hotspot analysis on the to-be-tested gate-level netlist to determine multiple candidate congestion hotspots.

[0054] Specifically, the data processing device can perform congestion hotspot analysis on the to-be-tested gate-level netlist to determine multiple candidate congestion hotspots. Among them, the candidate congestion hotspots may refer to the congestion hotspots generated due to various reasons (not limited to the combinational logic structure).

[0055] Optionally, in step S210, as an implementation manner, the data processing device can implement the congestion hotspot analysis on the to-be-tested gate-level netlist by means of pre-routing and placement, so as to determine multiple candidate congestion hotspots.

[0056] Figure 4 It is a flowchart of the congestion hotspot analysis method according to an embodiment of the present invention. It should be understood that by executing the congestion hotspot analysis method as Figure 4 shown, the data processing device can implement the congestion hotspot analysis on the to-be-tested gate-level netlist by means of pre-routing and placement, so as to determine the candidate congestion hotspots, that is, implement the above step S210.

[0057] AsFigure 4 As shown in the figure, the congestion hot spot analysis method may specifically include the following steps:

[0058] Step S211: Perform pre-routing layout according to the to-be-tested gate-level netlist to obtain pre-routing layout data.

[0059] Specifically, the data processing device may perform pre-routing layout according to the to-be-tested gate-level netlist to obtain pre-routing layout data.

[0060] It should be noted that the routing layout may refer to the process of converting a gate-level netlist into an actual circuit layout. Here, in order to perform congestion hot spot analysis, the data processing device will perform pre-routing layout on the to-be-tested gate-level netlist. Optionally, in step S211, the implementation of the pre-routing layout may be achieved by the data processing device by calling the functions in the electronic design automation software, and the present application does not limit this.

[0061] Step S212: Determine the multiple candidate congestion hot spots according to the pre-routing layout data.

[0062] Specifically, after obtaining the pre-routing layout data, the data processing device may determine the multiple candidate congestion hot spots according to the pre-routing layout data.

[0063] It should be understood that the congestion hot spot analysis method given above is only for illustration. In the actual application process, the data processing device may also adopt other methods to perform congestion hot spot analysis on the to-be-tested gate-level netlist under the design of relevant personnel, and the present application does not limit this. For example, the data processing device may also input the to-be-tested gate-level netlist into a pre-trained congestion hot spot analysis model to use the congestion hot spot analysis model to perform congestion hot spot analysis on the to-be-tested gate-level netlist. Among them, the congestion hot spot analysis model may be a model that can predict and determine congestion hot spots according to the gate-level netlist. The congestion hot spot analysis model may be trained using the gate-level netlists with congestion hot spot annotations. Optionally, the congestion hot spot analysis model may be a neural network model or other types of models, and the present application does not limit this.

[0064] Step S220: Display the multiple candidate congestion hot spots.

[0065] Specifically, the data processing device may display the multiple candidate congestion hot spots to the user.

[0066] Optionally, in step S220, as a way of displaying candidate congestion hotspots, the data processing device may first display the gate-level netlist to be tested, and then identify the logic units and the connection relationships between the logic units involved in each candidate congestion hotspot in the displayed gate-level netlist to be tested, so as to display each candidate congestion hotspot. Alternatively, as another way of displaying candidate congestion hotspots, if pre-routed layout data has been generated in advance during the congestion hotspot analysis process, then the data processing device may also display the pre-routed layout data in the form of a circuit diagram, and then identify the circuit areas covered by each candidate congestion hotspot in the circuit diagram, so as to display each candidate congestion hotspot. It should be understood that the above two ways of displaying candidate congestion hotspots are only for illustration. In actual application, the data processing device may also adopt other ways to display each candidate congestion hotspot under the design of relevant personnel, and this application does not limit this.

[0067] Step S230: Receive the combinational logic congestion hotspot selection instruction.

[0068] Specifically, the data processing device may support the user to select the displayed candidate congestion hotspots. The user's selection operation on the displayed candidate congestion hotspots may trigger a code statement selection instruction. The data processing device may then receive the logic congestion hotspot selection instruction triggered by the user.

[0069] Step S240: Determine the corresponding candidate congestion hotspot as the combinational logic congestion hotspot according to the combinational logic congestion hotspot selection instruction.

[0070] Specifically, after receiving the logic congestion hotspot selection instruction triggered by the user, the data processing device may determine the corresponding candidate congestion hotspot (that is, the candidate congestion hotspot selected by the user) as the combinational logic congestion hotspot according to the combinational logic congestion hotspot selection instruction.

[0071] It should be understood that the above way of determining the combinational logic congestion hotspot is only for illustration. In actual application, the data processing device may also adopt other ways to determine the combinational logic congestion hotspot under the design of relevant personnel, and this application does not limit this.

[0072] Step S300: Determine the code statement to be modified in the register transfer level code according to the combinational logic congestion hotspot.

[0073] Specifically, after determining the combinational logic congestion hotspot, the data processing device may determine the code statement to be modified in the register transfer level code according to the combinational logic congestion hotspot. Among them, the code statement to be modified only supports being converted into a combinational logic structure during the logic synthesis process.

[0074] It should be noted that depending on the writing method, the selected code statements may only support being converted into a combinational logic structure, may only support being converted into a multiplexer structure, or may support being converted into a combinational logic structure or a multiplexer structure (that is, both support being converted into a combinational logic structure and support being converted into a multiplexer structure) during the logic synthesis process. In this embodiment, in order to solve the wiring congestion problem by reducing the combinational logic structure in the gate-level netlist, the data processing device can determine the selected code statements that only support being converted into a combinational logic structure during the logic synthesis process in the register transfer level code and use them as the code statements to be modified.

[0075] Optionally, in step S300, as an implementation manner, the data processing device can determine the code statements to be modified in the register transfer level code according to the user's instruction.

[0076] Figure 5 It is a flowchart of the method for determining the code statements to be modified in the embodiments of the present invention. It should be understood that by executing the method for determining the code statements to be modified as Figure 5 shown, the data processing device can determine the code statements to be modified in the register transfer level code according to the user's instruction, that is, implement the above step S300. As Figure 5 shown, the method for determining the code statements to be modified can specifically include the following steps:

[0077] Step S310: Determine the code statements corresponding to each of the combinational logic congestion hotspots in the register transfer level code.

[0078] Specifically, the data processing device can determine the code statements corresponding to each combinational logic congestion hotspot in the register transfer level code. Optionally, in this step, the manner in which the data processing device determines the code statements corresponding to each combinational logic congestion hotspot in the register transfer level code can be implemented by calling the corresponding function in the electronic design automation software, and this application does not limit this. For example, the data processing device can determine the code statements corresponding to each combinational logic congestion hotspot in the register transfer level code by calling the cross_probe (cross detection) function. Among them, Cross-Probe is a debugging technology that allows users to cross-reference between different levels of design representations.

[0079] Step S320: Display the code statements corresponding to each of the combinational logic congestion hotspots.

[0080] Specifically, after determining the code statements corresponding to each combinational logic congestion hotspot, the data processing device can display the code statements corresponding to each combinational logic congestion hotspot to the user.

[0081] Step S330: Receive a code statement selection instruction.

[0082] Specifically, the user can perform a selection operation among the displayed code statements. The user's selection operation on the code statements can trigger a code statement selection instruction. The data processing device can then receive the code statement selection instruction triggered by the user.

[0083] Step S340: Determine the code statement corresponding to the code statement selection instruction as the code statement to be modified.

[0084] Specifically, after receiving the code statement selection instruction triggered by the user, the data processing device can determine the code statement corresponding to the code statement selection instruction (i.e., the code statement selected by the user) as the code statement to be modified.

[0085] Step S400: For each of the code statements to be modified, modify the code statement to be modified into a target code statement, where the target code statement supports being converted into a multiplexer structure during the logic synthesis process.

[0086] Specifically, after determining each code statement to be modified, for each code statement to be modified, the data processing device can modify the code statement to be modified into a target code statement. Among them, the target code statement is the same as the code statement to be modified in the expressed logic, but compared with the code statement to be modified, the target code statement supports being converted into a multiplexer structure during the logic synthesis process.

[0087] Optionally, the logic synthesis process includes an unfolding stage and a mapping stage. The unfolding stage involves unfolding high-level register transfer level code into a general technology library (GTECH library). The mapping stage involves mapping the register transfer level code unfolded into the general technology library to each logic unit in the general technology library. In the unfolding stage, a select code statement is usually unfolded into a select operation (i.e., SELECT_OP) or a multiplexer operation (i.e., MUX_OP). Among them, the select operation can only be mapped to a combinational logic structure in the mapping stage, while the multiplexer operation can be mapped to a combinational logic structure or a multiplexer structure (i.e., it can be mapped to a combinational logic structure or a multiplexer structure). In this embodiment, the code statement to be modified can specifically refer to a select code statement that is unfolded into a select operation in the unfolding stage. The target code statement can specifically refer to a select code statement that is the same as the code statement to be modified in the expressed logic but can be unfolded into a multiplexer operation in the unfolding stage.

[0088] Optionally, in step S400, as an implementation manner, the data processing device can modify the code statement to be modified into a target code statement according to the user's instruction.

[0089] Figure 6 This is a flowchart of the code statement modification method according to an embodiment of the present invention. It should be understood that by executing the code statement modification method as Figure 6 shown, the data processing device can modify the code statement to be modified into the target code statement according to the user's instruction. As Figure 6 shown, the code statement modification method may specifically include the following steps:

[0090] Step S410: Display the code statement to be modified.

[0091] Specifically, the data processing device can display the code statement to be modified to the user.

[0092] Step S420: Receive a statement modification instruction.

[0093] Specifically, the user can modify the displayed code statement to be modified. The modification operation of the user on the code statement to be modified can trigger a statement modification instruction. The data processing device can then receive the statement modification instruction triggered by the user.

[0094] Step S430: Modify the code statement to be modified into the target code statement according to the statement modification instruction.

[0095] Specifically, after receiving the statement modification instruction, the data processing device can modify the code statement to be modified into the target code statement according to the statement modification instruction.

[0096] It should be understood that the above-given code statement modification method is only for illustration. In actual application, the data processing device can also adopt other methods to modify the code statement to be modified into the target code statement under the design of relevant personnel. For example, the data processing device can also modify the code statement to be modified into the target code statement by calling a large language model with the ability of code writing and modification according to a pre-set template (this template is used to guide the model to generate an output that meets the expectations).

[0097] Step S500: Regenerate the target gate-level netlist according to the modified register transfer level code.

[0098] Specifically, after each code statement to be modified in the register transfer level code is modified into the target code statement, the data processing device can regenerate the target gate-level netlist according to the modified register transfer level code. It should be understood that in step S500, the process of the data processing device regenerating the target gate-level netlist according to the modified register transfer level code is the same as the process of generating the gate-level netlist to be tested according to the initially input register transfer level code given above, and will not be elaborated here.

[0099] Optionally, after regenerating the target gate-level netlist, the user can choose to end the current logic synthesis process and perform subsequent placement and routing processes based on the target gate-level netlist. Alternatively, the user can also choose to trigger the congestion hot spot analysis instruction again to obtain the congestion hot spot analysis service again. It should be understood that here, when the user triggers the congestion hot spot analysis instruction again, the data processing device can return to step S100 and re-execute steps S100 - S500 to provide the congestion hot spot analysis service to the user again. At the same time, it should be noted that during the new round of providing the congestion hot spot analysis service, the target gate-level netlist will be used as the new gate-level netlist to be tested.

[0100] Optionally, although converting the combinational logic structure in the gate-level netlist into a multiplexer structure can avoid the occurrence of wiring congestion problems, however, due to the disadvantages of large area and slow speed of the multiplexer structure itself, too many multiplexer structures will also have a negative impact on the power consumption, performance, and area of the formed chip. In the actual application process, only when the number of combinational logic structures and the number of multiplexer structures in the gate-level netlist are within a balanced range can it be ensured that neither wiring congestion problems will occur nor will there be a negative impact on the power consumption, performance, and area of the formed chip. Based on this, in this embodiment, the data processing device can also support the user to precisely control the number of multiplexer structures in the target gate-level netlist. Further optionally, the mapping direction of the multiplexer selection operation in the mapping stage is usually not determined. As a control method for the number of multiplexer structures, the data processing device can set mapping indication information for each target code statement according to the user's instruction, and precisely control the number of multiplexer structures in the target gate-level netlist according to the mapping indication information. Among them, the mapping indication information can be used to indicate the mapping direction of the target code statement during the logic synthesis process.

[0101] Figure 7 It is a flowchart of the target gate-level netlist generation method according to an embodiment of the present invention. By executing the Figure 7 target gate-level netlist generation method as shown, the data processing device can set mapping indication information for each target code statement according to the user's instruction, and precisely control the number of multiplexer structures in the target gate-level netlist according to the mapping indication information, thereby generating a target gate-level netlist that meets the requirements, that is, implementing the above step S500. As Figure 7 shown, the target gate-level netlist generation method may specifically include the following steps:

[0102] Step S510: Receive a mapping indication information setting instruction.

[0103] Specifically, the data processing device can receive a mapping indication information setting instruction. Among them, the mapping indication information setting instruction may include the user's structural transformation requirements for the target code statements during the logic synthesis process.

[0104] Step S520: Determine the mapping indication information corresponding to each of the target code statements according to the mapping indication information setting instruction.

[0105] Specifically, after receiving the mapping indication information setting instruction, the data processing device can determine the mapping indication information corresponding to each target code statement according to the mapping indication information setting instruction.

[0106] Optionally, since the selected code statements are usually expanded in a certain format during the expansion stage, in order to enable the data processing device to locate the multiplexer operations expanded by each target code statement after the expansion stage ends. The mapping indication information may include a standard expression. The standard expression can be used to locate the multiplexer operations expanded by each target code statement during the expansion stage. And, in order to enable the data processing device to indicate the mapping direction of the multiplexer operations expanded by each target code statement during the mapping stage. The mapping indication information may also include a mapping attribute. The mapping attribute can be used to indicate the mapping direction.

[0107] Step S530: Perform logic synthesis according to the modified register transfer level code and the mapping indication information corresponding to each of the target code statements to regenerate the target gate-level netlist.

[0108] Specifically, when determining the mapping indication information corresponding to each target code statement, the data processing device can perform logic synthesis according to the modified register transfer level code and the mapping indication information corresponding to each target code statement to regenerate the target gate-level netlist.

[0109] Optionally, in order to obtain a target gate-level netlist that meets the requirements, the user usually needs to try multiple rounds of adjustments. In order to enable the user to clearly understand the impact of each round of adjustment process on the power consumption, performance, and area of the formed chip, the data processing device can also generate and display corresponding evaluation data to the user.

[0110] Figure 8 It is a flowchart of the evaluation data display method according to an embodiment of the present invention. By executing the Figure 8 evaluation data display method as shown, the data processing device can generate and display corresponding evaluation data to the user. As Figure 8 shown, the evaluation data display method may specifically include the following steps:

[0111] Step S610: Receive an evaluation instruction.

[0112] Specifically, the user can trigger an evaluation instruction, and the data processing device can receive the evaluation instruction triggered by the user.

[0113] Step S620: Evaluate the power consumption, performance, and area of the formed chip according to the target gate-level netlist to obtain evaluation data.

[0114] Specifically, when receiving the evaluation instruction, the data processing device can evaluate the power consumption, performance, and area of the formed chip according to the target gate-level netlist to obtain evaluation data. Optionally, in step S620, the evaluation of the power consumption, performance, and area of the formed chip by the data processing device can be implemented by invoking the functions in the electronic design automation software, and this application does not limit this.

[0115] Step S630: Display the evaluation data.

[0116] Specifically, after obtaining the evaluation data, the data processing device can display the evaluation data to the user.

[0117] In the embodiment of the present invention, after receiving the congestion hot spot analysis instruction, the congestion hot spot analysis is performed on the gate-level netlist to be tested to determine at least one combinational logic congestion hot spot, and the code statements to be modified are determined in the register transfer level code according to the combinational logic congestion hot spot, and then each code statement to be modified is modified into a target code statement, and further the target gate-level netlist is regenerated according to the modified register transfer level code. Among them, the code statements to be modified only support being converted into combinational logic structures during the logic synthesis process, and the target code statements support being converted into multiplexer structures during the logic synthesis process. Thus, the embodiment of the present invention can support the user to analyze and solve the wiring congestion problem during the logic synthesis process, thereby improving the chip design efficiency and reducing the negative impact on the power consumption, performance, and area of the formed chip during the process of solving the wiring congestion problem.

[0118] Figure 9 is a schematic diagram of the information interaction device according to the embodiment of the present invention. As Figure 9 shown, the information interaction device according to the embodiment of the present invention includes a receiving unit 91, a congestion hot spot determination unit 92, a code statement to be modified determination unit 93, a code statement modification unit 94, and a gate-level netlist generation unit 95.

[0119] Specifically, the receiving unit 91 is used to receive the congestion hot spot analysis instruction;

[0120] The congestion hot spot determination unit 92 is used to perform congestion hot spot analysis on the gate-level netlist to be tested to determine at least one combinational logic congestion hot spot, and the combinational logic congestion hot spot is a congestion hot spot generated due to the combinational logic structure;

[0121] The code statement to be modified determination unit 93 is configured to determine a code statement to be modified in the register transfer level code according to the combinational logic congestion hot spot, and the code statement to be modified only supports being converted into a combinational logic structure during the logic synthesis process;

[0122] The code statement modification unit 94 is configured to modify each of the code statements to be modified into a target code statement, and the target code statement supports being converted into a multiplexer structure during the logic synthesis process;

[0123] The gate-level netlist generation unit 95 is configured to regenerate a target gate-level netlist according to the modified register transfer level code.

[0124] In the embodiment of the present invention, after receiving a congestion hot spot analysis instruction, a congestion hot spot analysis is performed on the gate-level netlist to be tested to determine at least one combinational logic congestion hot spot, and a code statement to be modified is determined in the register transfer level code according to the combinational logic congestion hot spot, and then each code statement to be modified is modified into a target code statement, and further a target gate-level netlist is regenerated according to the modified register transfer level code. Among them, the code statement to be modified only supports being converted into a combinational logic structure during the logic synthesis process, and the target code statement supports being converted into a multiplexer structure during the logic synthesis process. Thus, the embodiment of the present invention can support a user to analyze and solve the routing congestion problem during the logic synthesis process, thereby improving the chip design efficiency and reducing the negative impacts on the power consumption, performance, and area of the formed chip brought by the process of solving the routing congestion problem.

[0125] Figure 10 It is a schematic diagram of the electronic device according to the embodiment of the present invention. In this embodiment, the electronic device may specifically be the data processing device in the above embodiment. As Figure 10 shown, the electronic device: includes at least one processor 101; and, a memory 102 communicatively connected to at least one processor 101; and, a communication component 103 communicatively connected to the scanning device, and the communication component 103 receives and transmits data under the control of the processor 101; wherein, the memory 102 stores instructions executable by at least one processor 101, and the instructions are executed by at least one processor 101 to implement the above three-dimensional image generation method.

[0126] Specifically, the electronic device includes: one or more processors 101 and a memory 102, Figure 10 taking one processor 101 as an example. The processor 101 and the memory 102 may be connected through a bus or other means, Figure 10Take the bus connection as an example. As a non-volatile computer-readable storage medium, the memory 102 can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. By running the non-volatile software programs, instructions, and modules stored in the memory 102, the processor 101 executes various functional applications and data processing of the device, that is, implements the above three-dimensional image generation method.

[0127] The memory 102 may include a program storage area and a data storage area. Among them, the program storage area can store an operating system and application programs required for at least one function; the data storage area can store an option list, etc. In addition, the memory 102 may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, or other non-volatile solid-state storage devices. In some embodiments, the memory 102 may optionally include a memory remotely set relative to the processor 101, and these remote memories can be connected to an external device through a network. Examples of the above network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0128] One or more modules are stored in the memory 102 and, when executed by one or more processors 101, execute the three-dimensional image generation method in any of the above method embodiments.

[0129] The above product can execute the method provided in the embodiments of the present application, and has corresponding functional modules and beneficial effects for executing the method. For technical details not described in detail in this embodiment, reference can be made to the method provided in the embodiments of the present application.

[0130] In the embodiment of the present invention, after receiving a congestion hot spot analysis instruction, a congestion hot spot analysis is performed on the gate-level netlist to be tested to determine at least one combinational logic congestion hot spot, and the code statements to be modified are determined in the register transfer level code according to the combinational logic congestion hot spot, and then each code statement to be modified is modified into a target code statement, and then a target gate-level netlist is regenerated according to the modified register transfer level code. Among them, the code statements to be modified only support being converted into a combinational logic structure during the logic synthesis process, and the target code statements support being converted into a multiplexer structure during the logic synthesis process. Thus, the embodiment of the present invention can support users to analyze and solve the wiring congestion problem during the logic synthesis process, thereby improving the chip design efficiency and reducing the negative impacts on the power consumption, performance, and area of the formed chip during the process of solving the wiring congestion problem.

[0131] Another embodiment of the present invention relates to a non-volatile storage medium for storing a computer-readable program, and the computer-readable program is used for a computer to execute the above part or all of the method embodiments.

[0132] That is, those skilled in the art can understand that all or part of the steps in the methods of the above embodiments can be completed by instructing relevant hardware through a program. The program is stored in a storage medium and includes several instructions to enable a device (which can be a single-chip microcomputer, a chip, etc.) or a processor to execute all or part of the steps of the methods described in the embodiments of the present application. The foregoing storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard disks, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical discs.

[0133] The foregoing are only the preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, various modifications and changes can be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.

Claims

1. An information interaction method, characterized in that: The method comprises: Receive congestion hotspot analysis instructions; Performing a congestion hotspot analysis on the gate-level netlist to be tested to determine at least one combinational logic congestion hotspot, wherein the combinational logic congestion hotspot is a congestion hotspot generated by a combinational logic structure; Determining a code statement to be modified in a register transfer level code according to the combinational logic congestion hotspot, wherein the code statement to be modified only supports being converted into a combinational logic structure during a logic synthesis process; For each of the code statements to be modified, modify the code statement to be modified into a target code statement, wherein the target code statement supports being converted into a multiplexer structure during a logic synthesis process; Regenerate the target gate-level netlist based on the modified register-transfer-level code.

2. The method according to claim 1, characterized in that The logic synthesis process includes an expansion phase, the code statement to be modified is a selection code statement expanded into a selection operation in the expansion phase, and the target code statement is a selection code statement expanded into a multiplexer operation in the expansion phase.

3. The method according to claim 2, characterized in that The logic synthesis process further includes a mapping stage, in which the multiplexer operation is mapped into a combinational logic structure or a multiplexer structure; The regenerating the target gate-level netlist according to the modified register transfer level code comprises: Receive a mapping indication information setting instruction; Determine mapping indication information corresponding to each of the target code statements according to the mapping indication information setting instruction, wherein the mapping indication information is used to represent the structural conversion requirements of the target code statements during the logic synthesis process; Logic synthesis is performed according to the modified register transfer level code and the mapping indication information corresponding to each of the target code statements to regenerate the target gate level netlist.

4. The method according to claim 3, characterized in that The mapping indication information includes a standard expression and mapping attributes, and the standard expression is used to locate the multiplexer operation expanded by each target code statement in the expansion stage.

5. The method according to claim 1, characterized in that Before receiving the congestion hotspot analysis instruction, the method further includes: receiving the register transfer level code; Logic synthesis is performed on the register transfer level code to determine a gate-level netlist to be tested corresponding to the register transfer level code.

6. The method according to claim 1, characterized in that The performing congestion hotspot analysis on the gate-level netlist to be tested to determine at least one combinational logic congestion hotspot comprises: Performing congestion hotspot analysis on the gate-level netlist to be tested to determine a plurality of candidate congestion hotspots; displaying the plurality of candidate congestion hot spots; Receive a combinational logic congestion hotspot selection instruction; According to the combinatorial logic congestion hotspot selection instruction, the corresponding candidate congestion hotspot is determined as the combinatorial logic congestion hotspot.

7. The method according to claim 5, characterized in that The performing congestion hotspot analysis on the gate-level netlist to be tested to determine a plurality of candidate congestion hotspots comprises: Perform pre-wiring layout according to the gate-level netlist to be tested to obtain pre-wiring layout data; The plurality of candidate congestion hot spots are determined based on the pre-routing layout data.

8. The method according to claim 1, characterized in that Determining the code statement to be modified in the register transfer level code according to the combinational logic congestion hotspot comprises: Determining, in the register transfer level code, code statements corresponding to each of the combinatorial logic congestion hotspots; Displaying code statements corresponding to each of the combinational logic congestion hotspots; receiving a code statement selection instruction; The code statement corresponding to the code statement selection instruction is determined as the code statement to be modified.

9. The method according to claim 1, characterized in that: The modifying the code statement to be modified into a target code statement comprises: Display the code statement to be modified; Receive statement modification instructions; The code statement to be modified is modified into the target code statement according to the statement modification instruction.

10. The method according to claim 1, characterized in that After regenerating the target gate-level netlist according to the modified register transfer level code, the method further includes: Receive assessment instructions; Evaluate the power consumption, performance and area of ​​the formed chip according to the target gate-level netlist to obtain evaluation data; The evaluation data is presented.

11. An information interaction device, characterized in that: The device comprises: A receiving unit, used for receiving a congestion hot spot analysis instruction; A congestion hotspot determination unit, configured to perform congestion hotspot analysis on a gate-level netlist to be tested to determine at least one combinational logic congestion hotspot, wherein the combinational logic congestion hotspot is a congestion hotspot generated by a combinational logic structure; A code statement to be modified determining unit, used for determining a code statement to be modified in a register transfer level code according to the combinational logic congestion hotspot, wherein the code statement to be modified only supports being converted into a combinational logic structure during a logic synthesis process; A code statement modification unit, configured to modify each of the code statements to be modified into a target code statement, wherein the target code statement supports being converted into a multiplexer structure during a logic synthesis process; The gate-level netlist generation unit is used to regenerate a target gate-level netlist according to the modified register transfer level code.

12. A computer-readable storage medium storing computer program instructions, characterized in that: The computer program instructions implement the method according to any one of claims 1 to 10 when executed by a processor.

13. An electronic device, characterized in that: The device comprises: a memory for storing one or more computer program instructions; A processor, wherein the one or more computer program instructions are executed by the processor to implement the method according to any one of claims 1 to 10.

14. A computer program product, characterized in that When the computer program product is run on a computer, the computer is caused to execute the method according to any one of claims 1 to 10.

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