The application relates to an
FPGA prototype verification method and
system of a
smart meter chip, and belongs to the field of
integrated circuit testing and
electric power metering. The method aims to solve the problems of ASIC design
transplantation to an FPGA platform, large difference between a
verification environment and a real
power grid, and lack of a real-time closed-loop
verification mechanism. A technical scheme efficiently transplants the design to the FPGA by optimizing ASIC front-end synthesis constraints and adopting a
netlist-level IP replacement strategy; a hardware-in-the-loop
system is constructed, which comprises a real
power grid signal source, a separation
device simulation front end, an FPGA verification board, a high-precision standard
electric energy meter and a host computer. The
system can generate a real
power grid excitation and realize synchronous collection of prototype output and the standard meter, real-
time error analysis and dynamic adjustment of parameters, thereby forming a closed-loop verification. The application significantly improves code
transplantation efficiency, provides a highly consistent real power grid verification environment, and greatly improves verification iteration and defect positioning speed.