Implementing asynchronous first-in first-out data transmission by double-port direct access storage device

An asynchronous data, dual-port technology, applied in the direction of static memory, digital memory information, information storage, etc., can solve the problems of unfavorable data transmission performance, can not fully and accurately reflect the internal state of FIFO, and achieve the effect of improving efficiency

Inactive Publication Date: 2005-01-05
北京中科算源资产管理有限公司
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Problems solved by technology

[0002] Generally speaking, synchronous FIFO ((First-In First-Out)) has a simple structure and is easy to implement; the control logic of asynchronous FIFO is relatively complicated, and there are many special products on the market, but

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  • Implementing asynchronous first-in first-out data transmission by double-port direct access storage device
  • Implementing asynchronous first-in first-out data transmission by double-port direct access storage device
  • Implementing asynchronous first-in first-out data transmission by double-port direct access storage device

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Embodiment Construction

[0011] Using dual-port RAM to construct bridge FIFO in asynchronous data transmission can be divided into two steps to realize asynchronous FIFO.

[0012] The first step is to construct a general-purpose synchronous FIFO with dual-port RAM, such as Figure 1 As shown, all the signals in the figure work in one clock domain, and the clock domain is the same as the higher speed of the two external clock sources (both sides of data transmission).

[0013] The second step is to use a smaller register array to form an asynchronous interface on top of the common synchronous FIFO. The width of the register array is equal to the data width of the FIFO, and a status flag register is added; the depth of the register array is determined according to the gap ratio of the asynchronous clock domain. In fact, a register array with a depth of n is a small FIFO formed by connecting n register arrays with a depth of 1 in series. Therefore, the register array with a depth of 1 is defined as a reg...

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Abstract

The invention relates to a method for realizing asynchronous FIFO data transmission with dual port random access memory. The invention designs a bridge FIFO for asynchronous data transmission, the new FIFO is based on dual port RAM, the dual port RAM is packaged into a universal synchronous FIFO through synchronous control logic, and then uses a small register array to form an asynchronous interface. The steps are: S1: uses dual port RAM to form a universal asynchronous FIFO, S2: determines the data clock region, S3: reads the data, S4: realizes asynchronous data transmission. The FIFO designed with the invention, it can provide the quantity of data in FIFO accurately, thus the two sides of the data transmission can start data reading and writing operations and it upgrades the data transmission efficiency effectively.

Description

technical field [0001] The invention relates to the technical field of application-specific integrated circuit (ASIC) design and digital circuit design, in particular to a method for realizing asynchronous first-in-first-out data transmission by using a dual-port random access memory. Background technique [0002] Generally speaking, synchronous FIFO ((First-In First-Out)) has a simple structure and is easy to implement; the control logic of asynchronous FIFO is relatively complicated, and there are many special products on the market, but only the FIFO can be given. The three states of Full, Half-Full and Empty cannot fully and accurately reflect the internal state of the FIFO, which limits its use and is not conducive to the improvement of data transmission performance. Contents of the invention [0003] The FIFO designed by the present invention is on the basis of dual-port RAM (Random-Access Memory, random-access memory), and the dual-port RAM is packaged into a genera...

Claims

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Application Information

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IPC IPC(8): G06F13/00G11C7/00
Inventor 张亮韩承德
Owner 北京中科算源资产管理有限公司
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