Implementing asynchronous first-in first-out data transmission by double-port direct access storage device

Abstract

The invention relates to a method for realizing asynchronous FIFO data transmission with dual port random access memory. The invention designs a bridge FIFO for asynchronous data transmission, the new FIFO is based on dual port RAM, the dual port RAM is packaged into a universal synchronous FIFO through synchronous control logic, and then uses a small register array to form an asynchronous interface. The steps are: S1: uses dual port RAM to form a universal asynchronous FIFO, S2: determines the data clock region, S3: reads the data, S4: realizes asynchronous data transmission. The FIFO designed with the invention, it can provide the quantity of data in FIFO accurately, thus the two sides of the data transmission can start data reading and writing operations and it upgrades the data transmission efficiency effectively.

Description

technical field [0001] The invention relates to the technical field of application-specific integrated circuit (ASIC) design and digital circuit design, in particular to a method for realizing asynchronous first-in-first-out data transmission by using a dual-port random access memory. Background technique [0002] Generally speaking, synchronous FIFO ((First-In First-Out)) has a simple structure and is easy to implement; the control logic of asynchronous FIFO is relatively complicated, and there are many special products on the market, but only the FIFO can be given. The three states of Full, Half-Full and Empty cannot fully and accurately reflect the internal state of the FIFO, which limits its use and is not conducive to the improvement of data transmission performance. Contents of the invention [0003] The FIFO designed by the present invention is on the basis of dual-port RAM (Random-Access Memory, random-access memory), and the dual-port RAM is packaged into a genera...

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Problems solved by technology

[0002] Generally speaking, synchronous FIFO ((First-In First-Out)) has a simple structure and is easy to implement; the control logic of asynchronous FIFO is relatively complicated, and there are many special products on the market, but only the FIFO can be given. The three states of Full, Half-Full, and Empty cannot fully and accurately reflect the internal state of the FIFO, which limits its use and is not conducive to the improvement of data transmission performance.

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