Multiple grid electrode neuron transistor, manufacturing method therefor and formed nerve network

A technology of transistors and neurons, which is applied in the field of multi-gate neuron transistors and their preparation methods and neural networks, can solve the problems of high power consumption, low power consumption that does not meet the requirements of the human brain, and cumbersome preparation processes, and achieve space The effect of high utilization

Active Publication Date: 2017-06-30
NANJING UNIV
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Problems solved by technology

However, such a complex circuit scheme is not only cumbersome to prepare, but also has relatively ...

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  • Multiple grid electrode neuron transistor, manufacturing method therefor and formed nerve network
  • Multiple grid electrode neuron transistor, manufacturing method therefor and formed nerve network
  • Multiple grid electrode neuron transistor, manufacturing method therefor and formed nerve network

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Embodiment Construction

[0028] The technical solutions of the present invention will be described in detail below with reference to the accompanying drawings.

[0029] like figure 2 As shown, a multi-gate neuron transistor includes a substrate Substrate, a floating gate electrode G0, a gate dielectric layer C0, a source electrode S, a drain electrode D, a channel layer Channel, at least three groups of capacitor memory layers C1-C3 and There are at least three groups of input gates G1-G3 corresponding thereto. The floating gate electrode is set on the substrate, the gate dielectric layer is set on the floating gate electrode, the channel layer is set on the gate dielectric layer, and the source electrode and the drain electrode are respectively set on the channel layer. Both ends; each group of capacitance memory layers and input gates are not in contact with the channel layer; in each group of capacitance memory layers and input gates, the capacitance memory layer is located on the gate dielectric...

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Abstract

The invention discloses a multiple grid electrode neuron transistor comprising source and drain electrodes, a channel, gate media, a floating gate electrode, a plurality of input grid electrodes and capacitance memory layers among the input grids and the gate media. All of the input grid electrodes and the gate media are jointly coupled onto the floating gate electrode via the capacitance memory layers, the channel is coordinately controlled to output a current, and a weighted computation function of neurons is simulated. The capacitance memory layers change in capacitance volume along with history of input grid voltage signals, and therefore plasticity of synaptic weight can be simulated. The invention also puts forward a manufacturing method for the multiple grid electrode neuron transistor and a nerve network which is formed via electric interconnection among a number of grid electrode neuron transistors. The multiple grid electrode neuron transistor is simple in structure and is convenient to manufacture and integrate, and the multiple grid electrode neuron transistor can hopefully be applied to the field of brain-like intelligent chips and the like.

Description

technical field [0001] The present invention relates to the field of semiconductor devices, in particular to a multi-gate neuron transistor, a preparation method thereof, and a formed neural network. Background technique [0002] The era of big data puts forward very high requirements for the ability of computers to process information, and the development of traditional von Neumann computers has encountered a bottleneck. Future computers need devices and chip architectures based on new instruction sets to meet the rapidly increasing information processing requirements in the era of big data. Compared with traditional von Neumann computers, the human brain stores and processes information in a distributed and parallel manner, which can better handle traditional "big data" problems such as perception, interaction, and recognition, and the overall energy consumption is very low. Low. Therefore, brain-like intelligence provides new ideas for the development of computer techno...

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Application Information

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IPC IPC(8): H01L29/78H01L29/423H01L21/336
Inventor 万青万相杨毅丰平邵枫杜培富
Owner NANJING UNIV
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