14 results about "Node (circuits)" patented technology

This invention discloses a method and apparatus for calculating the three-phase asymmetrical short-circuit current in a distribution network considering photovoltaic (PV) power. The method includes: before a fault, using power flow calculations to obtain the node voltage and injected current of each node, including the PV node, during normal operation; equating the power source to a current source and the load to an impedance based on Norton's equivalent; calculating the admittance matrix based on an equivalent circuit model after a three-phase asymmetrical short-circuit fault; and constructing a network equation for the PV short-circuit calculation node impedance suitable for Gaussian iteration; simultaneously establishing nonlinear piecewise expressions for the voltage and current of the renewable energy node; and solving for the current and voltage during a renewable energy fault using an iterative method to obtain the fault short-circuit current. By constructing the admittance matrix and corresponding voltage and current expressions for single-phase-to-ground short circuits and two-phase-to-phase short circuits, and using iterative calculations to derive the final result, the accuracy of the calculation is improved.

This invention discloses a high-speed, high-precision voltage descent monitoring circuit, solving the problem of accurate and timely monitoring of voltage descent phenomena in large-scale integrated circuits, belonging to the fields of digital integrated circuit design and power management. This invention provides an optimized design method for ring oscillator point circuits, using standard cell type, threshold, drive capability, and power consumption as variables to find the ring oscillator circuit design with the highest voltage sensitivity, improving the resolution of the voltage descent monitoring circuit; it provides a one-fold, compact ring oscillator layout design to ensure load balance between nodes; it provides a Nyquist counter design to count the number of times nodes flip over a period of time, improving the voltage monitoring range and solving the metastable sampling problem of traditional counters; and it provides a high-speed voltage quantization circuit that processes coarse and fine quantization in parallel, improving the maximum sampling rate and quantization rate of the voltage descent monitoring circuit.

Circuit arrangement for the galvanically isolated transmission of electrical energy from a primary side to a secondary side, - wherein a number of secondary circuits (3) are arranged on the secondary side, - wherein the secondary circuits (3) each comprise a secondary winding (12) of a transformer (1) which is connected to a first and a second output (14, 15) of the respective secondary circuit (3) at which, with reference to a respective secondary-side ground (13), a first and a second output voltage (U1, U2) are provided, - wherein a first diode (16) is arranged between the respective secondary winding (12) and the respective first output (14) and a second diode (17) is arranged between the respective secondary winding (12) and the respective second output (15), - wherein on the primary side a respective control input of a first and a second semiconductor switch (8, 10) is connected to a control device (11) by which the first and the second semiconductor switch (8, 10) are switched at a common operating frequency (f), such that during a period (T) corresponding to the operating frequency (f) the first semiconductor switch (8) is switched on for a first period (T1) and the second semiconductor switch (10) is switched on for a second period (T2), - wherein on the primary side a series connection of a primary winding (4) of the transformer (1) coupled to the secondary windings (12) of the secondary circuits (3) and a capacitor (5) is connected on one side to a primary-side ground (6) and on the other side to a primary-side node (7), - wherein the node (7) is connected on the one hand via the first semiconductor switch (8) to a voltage source (9) providing a primary-side supply voltage (U0) and on the other hand via the second semiconductor switch (10) to the primary-side ground (6), characterized in that - the primary winding (4) is connected to the primary-side node (7) and the capacitor (5) is connected to the primary-side ground (6), - that a capacitor voltage (UC) is tapped and supplied to the control unit (11) and - that the control device (11) is designed in such a way that it takes into account the tapped capacitor voltage (UC) when determining the ratio (α) of the first period (T1) to the second period (T2).

The invention relates to an electrical property test structure and a test method thereof, and relates to the technical field of integrated circuits, the structure comprises a test array which comprises a target transistor and a plurality of peripheral areas surrounding the target transistor and distributed along the radial direction of the test array, and the test array is configured to receive a test voltage according to the received test voltage; outputting the to-be-measured current generated by the target transistor and / or the plurality of peripheral regions; the gating device is connected with the target transistor and the plurality of peripheral areas and is configured to respond to a received gating signal, and at least one peripheral area is connected with the target transistor; and / or connecting the plurality of peripheral regions to adjust the current to be tested generated by the test array; wherein the test array comprises to-be-tested current of the peripheral area, and the to-be-tested current is in proportional relation with to-be-tested current only comprising the target transistor. The structure and the method are completely compatible with the existing processing technology, and are suitable for platforms with different technical nodes. The new structure designed by the method can eliminate the influence of test noise, and more accurate MOS electric leakage can be obtained.

This application relates to a one-dimensional non-Hermitian configuration circuit for realizing the non-Hermitian skin effect, belonging to the field of topology circuits. The circuit includes a first node, a second node, and a third node; the first node and the second node are connected via intra-cell capacitance, and the first node and the third node are connected in parallel via intra-cell capacitance and a first voltage follower branch; the second node and the third node are connected in parallel via intra-cell capacitance and a second voltage follower branch; one end of the third node is connected to an inter-cell capacitance; one end of the first node is connected to a first ground branch, and the other end of the first ground branch is grounded; one end of the second node is connected to a second ground branch, and the other end of the second ground branch is grounded; one end of the third node is connected to a third ground branch, and the other end of the third ground branch is grounded. This application solves the problem that the SSH model framework cannot achieve independent or coordinated control due to the inability to introduce multiple non-reciprocal couplings.

Low-latency communication system (100), including: a slave node transceiver (104), comprising: an upstream transceiver circuit (122) for receiving a first signal sent via a two-wire bus (106) from an upstream device and for providing a second signal via the two-wire bus (106) to the upstream device, a downstream transceiver circuit (124) for providing a third signal downstream via the two-wire bus (106) towards a downstream device and for receiving a fourth signal via the two-wire bus (106) from the downstream device and a peripheral device interface (127, 129) for receiving first data from a first peripheral device that is communicatively coupled to the peripheral device interface (127, 129), wherein the downstream transceiver circuits (124) are to receive the first data into the third signal and; wherein the first signal comprises second data generated by a second peripheral device (127, 129) communicatively coupled to the upstream device, wherein the third signal is provided downstream after the first signal has been received, and the third signal comprises less than all the second data generated by the second peripheral device (127, 129) communicatively coupled to the upstream device, and wherein the peripheral device interface (127, 129) of the first peripheral device, which is communicatively coupled with the peripheral device interface (127, 129), is to provide at least a part of the second data generated by the second peripheral device, which is communicatively coupled with the upstream device, and wherein the fourth signal includes third data generated by a third peripheral device communicatively coupled to the downstream device, the second signal is provided upstream after the fourth signal has been received, and the second signal includes less than all the third data generated by the third peripheral device communicatively coupled to the downstream device, and wherein the peripheral device interface of the first peripheral device, which is communicatively coupled to the peripheral device interface, is to provide at least some of the third data generated by the third peripheral device, which is communicatively coupled to the downstream device, and wherein adding the first data to the third signal comprises adding the first data within a number of data slots in a downstream part of a superframe, and wherein a mask register DNMASK0, DNMASK1, DNMASK2 and DNMASK3 is provided which provides one bit for each possible downstream data slot, and If a slot mask bit LDNSLOTS.DNMASKEN of the mask register is set, the slot mask bit LDNSLOTS.DNMASKEN is used to select which downstream slots are consumed by the first peripheral device communicatively coupled to the slave node transceiver (104), and these are placed in a TX frame buffer, and If the slot mask bit LDNSLOTS.DNMASKEN is not set, an LDNSLOTS register defines the number of downstream slots consumed by the slave node transceiver. where the LDNSLOTS register defines the number of downstream data slots, starting immediately after a synchronization control frame, SCF.

The invention discloses a modulation method for prolonging double-follow-current time and improving electric energy quality of ANPC topology. A single ANPC three-level topology circuit or a plurality of ANPC three-level topology circuits are arranged in parallel to form a topology structure; the set ANPC three-level topology circuit is monitored, the period of the AC side voltage of the ANPC three-level topology circuit is judged, and according to the period, the AC side voltage of the ANPC three-level topology circuit is monitored at a starting time node of a non-zero level state, an ending time node of the non-zero level state, a starting time node of zero level follow current and an ending time node of zero level follow current. And an inner tube, an outer tube and a clamping tube of the ANPC three-level topology circuit are correspondingly controlled to adjust the circuit. The beneficial effects of the invention are that on the basis of realizing double-loop follow current balanced loss, the technical problem that specific waves must be used under specific working conditions due to the fact that the double-loop follow current is modulated under different working conditions such as rectification, inversion, low power factor and the like in the prior art is solved.

The invention provides an electrical system diagram generation method and a cable loop path laying method and device, and relates to the technical field of electrical system data processing. The method comprises the steps of constructing an electrical system architecture diagram of a target electrical system in a building electrical model, establishing a model system association relationship through a corresponding relationship between a model identifier of a component in the model and a node identifier of a corresponding node in the architecture diagram, determining a target cabinet and determining a lower-level loop of the target cabinet in the electrical system architecture diagram, reading electrical parameters of a lower-level loop from engineering attribute information of the building electrical model to determine specification parameters of wires forming the lower-level loop, generating an electrical system diagram according to the information, and when the building electrical model is updated, updating the electrical system diagram according to the model system incidence relation and the electrical system architecture diagram. According to the method, the laying path of the cable loop path is determined according to the electrical system diagram, the electrical system diagram is generated, and when the model changes, the electrical system diagram is correspondingly updated.

This application discloses an online detection method and system for loose connections in excavator electrical circuits. The method includes: identifying the current working condition based on the acquired excavator operating status signal, and determining an adaptive threshold for the working condition, including a detection cycle and a high-frequency energy threshold; based on the detection cycle, calculating five characteristic parameters for each circuit based on the acquired multi-circuit signals, including the proportion of high-frequency energy, signal fluctuation coefficient, equivalent contact resistance change rate, voltage change rate extreme value, and amplitude jump amplitude; performing a preliminary loose connection judgment based on the characteristic parameters and corresponding thresholds, generating a suspected loose connection flag bit for the corresponding circuit, and obtaining a preliminary loose connection judgment result; based on the preliminary loose connection judgment result, performing a secondary verification based on the electrical topology to distinguish between loose connections at common nodes and single-circuit loose connections; if it is a single-circuit loose connection, determining the type of single-circuit loose connection based on the five characteristic parameters, namely, a contact oxidation type loose connection, a contact insufficient pressure type loose connection, or a terminal loose type loose connection.

A circuit includes at least one coupling node configured to be coupled, via a cable, to a load to transmit a supply voltage thereto. The circuit includes test circuitry configured to sense at least one sensing signal indicative of a value of the cable impedance and / or of the cable voltage across the cable, to perform a comparison between the at least one sensing signal and at least one threshold indicative either of a threshold resistance value for the cable impedance or indicative of a threshold voltage value for the cable voltage, produce a comparison signal as a result of the comparison.

This invention discloses a timing optimization post-processing method for RSFQ circuits, comprising the following steps: S1, performing topology analysis on the process-mapped RSFQ circuit netlist to determine the movable range of each node in the pipeline stage; S2-S3, fan-out-aware D flip-flop insertion strategy; S4, performing path balancing on unbalanced paths in the circuit netlist and updating the circuit netlist; S5-S6, a splitter structure optimization method based on node replication; S7, iteratively executing S2 to S3 and S5 to S6 until the worst-case stage delay converges or the set number of iterations is reached; S8, inserting splitters into the RSFQ circuit netlist, and finally outputting the optimized valid RSFQ circuit netlist. This method, without changing the circuit logic depth and functional correctness, restructures high fan-out nodes in the circuit, thereby reducing the splitter tree depth and lowering the worst-case stage delay.

The invention discloses a topology identification and line parameter correction method and system based on snow ablation optimization and a medium, and relates to the technical field of circuit topology identification. A whole-network electrical path matrix is constructed by using a cooperative change relationship between node injection power and voltage amplitude, and a causal relationship of electrical influence between nodes is revealed based on a basic physical law of a circuit. Starting from an end node, a grouping recursive algorithm based on a distance relation avoids the problem of combination explosion caused by global one-time search of all possible topological combinations; a large problem is decomposed into a local small problem in a recursion mode, the calculation efficiency is improved, the method is suitable for a large-scale transformer area, initial estimation of line parameters is synchronously carried out by utilizing information such as the electrical distance between nodes while the topological structure is recovered, and initial joint identification of topology and parameters is achieved; a natural ice and snow ablation process is simulated based on a snow ablation optimization algorithm, local optimum can be more effectively jumped out, and a parameter solution closer to real global optimum is found.

This invention discloses a multi-dimensional detection and location method and system for arc faults in building electrical circuits. The method injects low-amplitude broadband excitation signals into key nodes of the power distribution circuit using electromagnetic excitation and sensing devices, collects the line response waveform, and establishes a steady-state electromagnetic response baseline. Based on the baseline, autocorrelation calculations and spectrum analysis are performed to extract the resonance peak frequency, energy distribution, and bandwidth characteristics, generating an electromagnetic mode feature fingerprint. By constructing a time-frequency coupled resonance matrix, the frequency shift of the resonance peak and changes in the energy gradient are monitored in real time to identify abnormal resonance states of the line. After detecting an anomaly, a spatial location equation is established based on the phase distribution of multiple nodes, and a phase inversion algorithm is used to determine the location of the arc or breakdown source. The line stability coefficient is calculated by combining the location results with time-series resonance data to predict the arc risk level. When the risk level exceeds a threshold, an electromagnetic compensation module is activated to generate an opposite phase suppression signal and inject it into the abnormal area, achieving active protection closed-loop control.

The application relates to an electrical test structure and a test method thereof, and relates to the technical field of integrated circuits. The structure comprises a test array, a target transistor, and a plurality of peripheral regions surrounding the target transistor and distributed radially along the test array. The structure is configured to output a test current generated by the target transistor and / or the plurality of peripheral regions according to a received test voltage. A gate is connected to the target transistor and the plurality of peripheral regions. The gate is configured to connect at least one peripheral region to the target transistor in response to a received gate signal, and / or connect the plurality of peripheral regions to adjust the test current generated by the test array. The test current of the peripheral regions is in proportional relationship with the test current of the target transistor. The structure and the method are fully compatible with existing process technology and are suitable for platforms of different technology nodes. The new structure designed by the method can eliminate the influence of test noise and obtain more accurate MOS leakage.