38 results about "Node (circuits)" patented technology

Analysis of an electrical circuit is performed using a computer program product (60) and a method. In accordance with the program and the method, a electrical circuit analyzer generates an admittance matrix for an electrical circuit which is being analyzed. The admittance matrix includes symbolic expressions rather than numerical expressions for at least some components of the electrical circuit. The electrical circuit analyzer linearly and algebraically solves an equation system including the admittance matrix for analyzing at least a part of the electrical circuit. The electrical circuit analyzer uses symbolic computation to solve the equation system including the admittance matrix for analyzing at least a part of the electrical circuit. The equation system including the admittance matrix can be solved in various types of analyses, including (1) determining a transfer function between specified nodes of the electrical circuit; and (2) optimizing a component of the electrical circuit. The electrical circuit analyzer sets up the admittance matrix Y by following a set of “rules”. Special rules are provided for certain telecommunications components, such as multi-winded transformers, loading coils, line-drivers, analogue cables, and filters. Inclusion of these special rules for telecommunications components enables the electrical circuit analyzer to be more applicable to telecommunications circuits than conventional analyzers. In accordance with a block/subcircuit matrix approach, an overall circuit is divided into plural subcircuits. In such case, the admittance matrix can comprise separate admittance blocks for each of plural subcircuits. Connectivity blocks which represent connectivity between the plural subcircuits are situated on a cross diagonal of the admittance matrix. The admittance matrix can then be conveniently utilized for analyzing at least a part of the electrical circuit. Advantages of this approach include recursively reducing the size of the matrices including the admittance matrix as subcircuits are added to the admittance matrix.

The invention discloses an extension cone method capable of sensing the real-time situation of a power distribution network. According to the extension cone method, an extension cone planning model is established, real-time trend results such as the voltage amplitude value and the phase angle of nodes of the whole network are calculated, and the purpose of sensing the real-time situation of the power distribution network is achieved. The extension cone method comprises the following steps that first, net rack data are read, the net rack data comprise the connection relation of the nodes and branch circuits, real-time data returned by points which are provided with measuring devices and historical loads of points which are not provided with the measuring devices; second, a planning mathematical model is established, the planning mathematical model comprises an objective function model, a trend equation equality constraint, an inequality constraint of node voltages and load nodes; third, secondary cone planning processing is conducted on the trend equation equality constraint, the node voltages, node active power and node reactive power respectively, and state estimation models of an objective function, the equality constraint and the inequality constraint are obtained; fourth, the state estimation models are solved, so that the voltage amplitude of the nodes of the power distribution network and the trend information of the phase angle are obtained, and the purpose for sensing the real-time situation of the power distribution network is achieved.

The invention relates to a power system harmonic flow algorithm giving consideration to uncertainty and three-phase unbalance, and the algorithm comprises the steps: selecting a harmonic order h; calculating an h-th order harmonic current value of a harmonic source injection system connected with a nonlinear load node; building an h-th order harmonic model of system elements comprising all circuits and a transformer; initializing a harmonic voltage and phase angle of each node; setting the number of interaction times, and calculating the equivalent injection harmonic current value of each linear load node in each iteration process; solving the sum of the branch harmonic currents from a tail node, and obtaining the harmonic current value of each phase of each branch circuit; sequentially calculating the harmonic voltage values of the nodes from the head end of a feed line to the tail end of the feed line, wherein an iteration ending criterion is that the deviation of the harmonic voltage of each node at each phase relative to the value at the last iteration is less than an allowed value; and solving the distortion rate of the harmonic voltage of each node at each phase according to an obtained fundamental wave voltage value and the value of each harmonic voltage.

The communication bus system includes a plurality of node circuits (10a-d) and relay circuits (12, 14, 16) coupling the node circuits (10a-d). The relay circuits (12, 14, 16) have transceiver circuits (124, 164) for relaying messages (21) between the node circuits (10a-d) in normal mode. The transceiver circuits (124, 164) are powered down in the sleep mode. A detector circuit (120, 160) detects an incoming message (41) while the relay circuit (12, 14, 16) is in a sleep mode. The mode control circuit (122, 162) powers up the transceiver (124, 164) in response to detection of the incoming message (21). Steps are taken to ensure that in normal mode the message (21) will not be relayed in an unreadable form. The mode control circuit (122, 162) is arranged to cause the transceiver (124, 164) to relay the remainder (25) of the incoming message (21) after power-up. In one embodiment, the power required to transmit the remainder (25) of the incoming message (21) is drained from a capacitor (306) in the power supply (30) before the power supply (30) controls the supply voltage in normal mode. In another embodiment, the detector circuit (120, 160) temporarily controls the operation of the transceiver (124, 164) at the start of the normal mode instead of the additional detector (58a-d) which normally controls the direction of operation in the normal mode direction.

In a power source system, circuit units by the number of systems n or more are respectively connected correspondingly to power sources by the number of n (n is an integer of 2 or more). A common ground is all of the circuit units in common. A ground wiring portion establish node-to-node connection between (n+α) pieces of common ground nodes NC(1) to NC(n+α) provided in the common ground and (n+α) pieces of ground plane nodes NP(1) to NP(n+α) provided on a vehicle body in an independent manner, thereby enabling a simple configuration of redundant circuits that can withstand multipoint failures without separating the ground for each system.

Techniques for computer aided design and engineering of integrated circuits can use group identifiers of correlated signals and time delay values when using vectorless dynamic voltage drop (DVD) simulations and when using other types of simulations or analyses of a circuit design. A method in one embodiment can include the operations of: receiving a design representing an electrical circuit that includes a plurality of pins, the plurality of pins including one or more input nodes or one or more output nodes in the electrical circuit; identifying, in the design, one or more groups of pins that are correlated such that, within each identified group, all of the pins in the identified groups switch between voltage states in a correlated way; assigning, for each pin in each identified group, an identifier for the identified group and a time delay value based on the pin's delay from an initial point in the identified group's logic chain to the pin. The group identifier and the time delay at each pin can limit the switching activities in the DVD simulations to reduce pessimistic results from the simulations. Other methods are described, and data processing systems and machine readable media that cause such systems to perform these methods are also described.

The invention discloses a D latch with layout symmetry and resistance to three-node upset, and belongs to the field of anti-core reinforcement in reliability of integrated circuits. The problems thatan existing anti-three-node-overturn D latch needs to consume more hardware, and is high in power consumption and large in area are solved. The D latch comprises 44 NMOS transistors N1 to N44 and 20 PMOS transistors P1 to P20; and the transistors N1 to N16 and the transistors P1 to P8 form a unit 1, the transistors N17 to N32 and the PMOS transistors P9 to P16 form a unit 2, and the unit 1 and theunit 2 are mirror images of each other in circuit structure. Two units which are connected in a crossed mode are used for achieving recovery of overturning of all the three nodes. The D latch is mainly suitable for medium-low frequency circuits with low power consumption.

An integrated circuit including at least one circuit node, multiple duplicate circuit blocks integrated on the integrated circuit in close proximity with each other, each including at least one device that is susceptible to random telegraph noise (RTN), and a switch circuit that swaps electrical coupling of the duplicate circuit blocks, one at a time, to the at least one circuit node in sequential cycles of a clock signal. The duplicate circuit blocks may be large functional blocks, such as an oscillator or a comparator or the like, or limited to circuits including RTN susceptible devices, such as differential pairs or the like. Each duplicate circuit block may include any number of connections for coupling to corresponding circuit nodes. The swapping may further include chopping in which multiple inputs are swapped with each other while multiple outputs are swapped with each other in consecutive clock cycles.

The invention discloses a dual-node-upset-resistant D latch applied to a high-frequency circuit, which belongs to the field of anti-core reinforcement in reliability of integrated circuits. The problems that a traditional D latch resistant to charge sharing needs to consume more hardware and is large in power consumption and area, and the reinforcement performance is seriously affected due to moresensitive nodes are solved. The D latch comprises 20 NMOS transistors N1 to N20 and 12 PMOS transistors P1 to P12, and only 32 transistors are needed to construct the D latch, so that the area andthe power consumption overhead of the D latch are reduced. An input signal D can be directly transmitted to the output end of an output signal D through the transmission gates constructed by the transistors N20 and P12, so that the transmission delay is reduced. The D latch provided by the invention is suitable for being applied to high-frequency circuits, and is particularly suitable for aerospace, aerospace flight, nuclear power stations and the like with nuclear radiation effects.

The invention discloses an anti-charge sharing D latch for high-frequency circuit application, which belongs to the field of anti-radiation reinforcement in integrated circuit reliability. The problems of large hardware overhead, multiple sensitive nodes, high power consumption, long transmission time and long recovery time of an anti-charge sharing D latch applied to a high-frequency circuit aresolved. The gate of a transistor TN1 is connected to a node S8, the gate of a transistor TN2 is connected to a node S7, the gate of a transistor TN9 is connected to a node S4, and the gate of a transistor TN10 is connected to a node S3. Due to the above connection mode, the recovery time after overturning can be reduced, the transistors TP3 and TN1, TP4 and TN2, TP9 and TN9, and TP10 and TN10 areensured not to be influenced at the same time as much as possible, so that the overturned node can be recovered quickly, and the system can recover to a normal working state in a very short time. Therefore, the anti-charge sharing D latch for high-frequency circuit application is mainly applied to high-frequency circuits.

A precise IRDrop simulation method for a large-scale array circuit comprises the following steps: 1) dividing the array circuit to belong to different specified sub-regions according to an input region resistance process file; 2) initializing the data structure of the sub-region, and storing the position information of all unit circuits covered by the sub-region; 3) respectively extracting parasitic resistance of each sub-region; 4) generating netlist information of all circuits in the sub-region; 5, voltage and current equations of all nodes in the array circuit are established, node voltage and current information is solved and calculated, and IRDrop effect analysis is carried out on the array.According to the accurate IRDrop simulation method for the large-scale array circuit, an accurate IRDrop simulation result can be provided for circuit designers, and the influence brought by the IRDrop effect is accurately analyzed.

The invention relates to a thread processing method in the field of integrated circuits, in particular to an integrated circuit resistance extraction method based on a parallel algorithm. The method comprises the following steps of: 1, reading layout information, and storing all conductors in corresponding units according to coordinates of the conductors or via holes and layers to which the conductors or via holes belong; step 2, firstly, establishing a thread pool, and establishing a task adding thread pool for each conductor layer of each unit; then, starting threads according to the thread number configured by a user, and performing the following operations on each thread: step two, taking out a task from a thread pool; step 2, traversing all conductors in the task, and creating nodes at places in contact with other conductors or via holes; step 2, returning the created nodes and conductors or via holes corresponding to the nodes to the host process; and step 3, all the threads run to the end, all the nodes are stored in the conductor, and the repeated nodes are deleted.

Embodiments of the present disclosure generally relate to circuits and methods including configuration terminals. Circuits and methods are provided, where a configuration terminal (12) of the circuit(10) is coupled to an internal node (15) during a configuration phase and decoupled from the internal node (15) during normal operation.