Low-redundancy charge sharing resistant D latch for high frequency circuit applications

A high-frequency circuit, charge sharing technology, applied in logic circuits, electrical components, reliability improvement and modification, etc., can solve the problems of long transmission time, large layout area, and high power consumption

Active Publication Date: 2020-04-14
ZHONGBEI UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The present invention aims to solve the problems of large hardware overhead, large layout area, high power consumption, and long transmission time in the anti-charge sharing D latch reinforced by multi-mode redundancy in the prior art. The present invention provides a Low Redundancy and Charge-Sharing Resistant D-Latch for High-Frequency Circuit Applications

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  • Low-redundancy charge sharing resistant D latch for high frequency circuit applications
  • Low-redundancy charge sharing resistant D latch for high frequency circuit applications

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Embodiment Construction

[0080] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0081] It should be noted that, in the case of no conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other.

[0082] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but not as a limitation of the present invention.

[0083] see figure 1 Describe this embodiment mode, the low-redundancy and anti-charge-sharing D latch orie...

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Abstract

The invention discloses a low-redundancy D latch capable of resisting charge sharing for high-frequency circuit application, and belongs to the field of radiation hardening in integrated circuit reliability. The problems of high hardware overhead, large layout area, high power consumption and long transmission time of an anti-charge sharing D latch reinforced by adopting multimode redundancy in the prior art are solved; a transistor TP1 is connected with a node S8, a transistor TP2 is connected with a node S7, a transistor TP9 is connected with a node S4, and a transistor TP10 is connected with a node S3. Such a connection mode is beneficial for the transistors TP1 and TN3, the transistors TP2 and TN4, the transistors TP9 and TN9, and the transistors TP10 and TN10 not to be influenced on or off at the same time as much as possible. And the recovery time after the node is overturned is reduced as much as possible, and the influence on the whole circuit system can also be reduced as muchas possible. The low-redundancy charge sharing resistant D latch is mainly applied to high-frequency circuits.

Description

technical field [0001] The invention belongs to the field of anti-radiation reinforcement in integrated circuit reliability. Background technique [0002] With the continuous advancement of technology, integrated circuits have been widely used in various fields. At the same time, its application in important fields such as deep space exploration, medical equipment, aerospace, and automotive electronics has put forward higher requirements for its reliability. Energetic particles in a radiation environment deposit charges on their tracks as they pass through sensitive regions of microelectronic devices, and these charges change the stored value in memory elements such as latches. With the rapid development of semiconductor technology, the feature size of integrated circuits is continuously reduced, and the operating voltage is continuously reduced, resulting in the continuous reduction of the node capacitance of the circuit, so that the amount of charge (critical charge) requ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K19/003
CPCH03K19/00338H03K19/00315
Inventor 郭靖蔡宣明
Owner ZHONGBEI UNIV
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