c 2 mos trigger

A technology of flip-flops and inverters, applied in electric pulse generator circuits, bipolar transistors to generate pulses, etc., can solve the problems of inability to achieve high-speed operation data integrity, limited operating frequency, etc., and achieve a small number, leakage and power consumption. Low, cost-saving effect

Active Publication Date: 2022-05-20
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The disadvantages of this traditional D flip-flop are: the operating frequency is limited, it cannot achieve high-speed operation and maintain data integrity

Method used

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  • c <sup>2</sup> mos trigger
  • c <sup>2</sup> mos trigger
  • c <sup>2</sup> mos trigger

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0019] see figure 2 As shown, in the following embodiment, the C2MOS flip-flop includes: five PMOS transistors PM1-PM5, eight NMOS transistors NM1-NM8 and three inverters FX1-FX3.

[0020] The sources of the PMOS transistors PM1 to PM3 are connected to the power supply voltage terminal VDD, the drain of the PMOS transistor PM1 is connected to the source of the PMOS transistor PM5, the drains of the PMOS transistors PM5 and PM3 are connected to the drain of the NMOS transistor NM1, and the PMOS transistor The gate of PM2 is connected to the gate of NMOS transistor NM5, and the connected node is denoted as X.

[0021] The NMOS transistor NM2 and the NMOS transistor NM3 are connected in series between the source of the NMOS transistor NM1 and the ground.

[0022] The gate of the PMOS transistor PM1 and the gate of the NMOS transistor NM2 are used as the input terminal D of the flip-flop, and the gate of the PMOS transistor PM3 and the gate of the NMOS transistor NM3 input an in...

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PUM

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Abstract

The invention discloses a C 2 MOS flip-flops, including: five PMOS transistors, eight NMOS transistors and three inverters; when the clock signal CK is at a high level, the state of node X is collected to node Y, and passed through the first inverter and the second inverter The three inverters are transmitted to the output terminal Q, and the feedback loop does not work at this time; when the clock signal CK is low, the state of the input node D is collected to the node X, and the first inverter, the second inverter 1. The feedback loop composed of the seventh NMOS transistor and the eighth NMOS transistor maintains the state of the node Y, so that the output state of the output terminal Q remains unchanged. The invention can make the circuit run in the high-speed digital circuit and maintain the integrity of the data.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuits, in particular to a C 2 MOS (synchronous CMOS logic) flip-flops. Background technique [0002] D flip-flop is a very important circuit structure, often used in frequency divider, data recovery and other circuit structures. [0003] Existing conventional D flip-flops such as figure 1 As shown, it consists of 7 inverters, 4 MOS transistors and two NAND gates. [0004] The disadvantages of this traditional D flip-flop are: the operating frequency is limited, and it cannot realize high-speed operation and maintain data integrity. Contents of the invention [0005] The technical problem to be solved by the present invention is to provide a C2MOS flip-flop, which can make the circuit run in a high-speed digital circuit and maintain data integrity. [0006] In order to solve the above technical problems, the C2MOS flip-flop of the present invention includes: five PMOS transistors, e...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K3/28
CPCH03K3/28
Inventor 曹亚历邵博闻
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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