IRDrop simulation method for large-scale array circuit

A simulation method and large-scale technology, applied in electrical digital data processing, special data processing applications, instruments, etc., which can solve the problems of large differences in circuit IRDrop simulation results and uneven parasitic resistance.

Pending Publication Date: 2022-03-15
成都华大九天科技有限公司
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, due to the inhomogeneity of the semiconductor process, the resistance characteristics of each area in the array circuit are different, and the parasitic resistance is also different in each area, and due to the difference in temperature and other environments in different areas, the par

Method used

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  • IRDrop simulation method for large-scale array circuit
  • IRDrop simulation method for large-scale array circuit
  • IRDrop simulation method for large-scale array circuit

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Experimental program
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Embodiment 1

[0029] figure 1 For the flow chart of the IRDrop simulation method according to the large-scale array circuit of the present invention, reference will be made below figure 1 , the IRDrop simulation method of the large-scale array circuit of the present invention is described in detail.

[0030] First, in step 101, the initial netlist information unit netlist of the unit circuit Unit is established.

[0031] In the embodiment of the present invention, the netlist information includes: all unit circuit port node information, all unit circuit internal node information, all resistance information connected to different nodes, and all active device information.

[0032] In step 102, according to the input area resistance process file, the array circuits are divided into different specified sub-areas.

[0033] In the embodiment of the present invention, the sub-regions are numbered after dividing the array circuit into different specified sub-regions, as in figure 2 As shown, th...

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Abstract

A precise IRDrop simulation method for a large-scale array circuit comprises the following steps: 1) dividing the array circuit to belong to different specified sub-regions according to an input region resistance process file; 2) initializing the data structure of the sub-region, and storing the position information of all unit circuits covered by the sub-region; 3) respectively extracting parasitic resistance of each sub-region; 4) generating netlist information of all circuits in the sub-region; 5, voltage and current equations of all nodes in the array circuit are established, node voltage and current information is solved and calculated, and IRDrop effect analysis is carried out on the array.According to the accurate IRDrop simulation method for the large-scale array circuit, an accurate IRDrop simulation result can be provided for circuit designers, and the influence brought by the IRDrop effect is accurately analyzed.

Description

technical field [0001] The invention relates to the technical field of post-simulation design of semiconductor circuits in the automation of semiconductor integrated circuits, in particular to an IRDrop simulation method for large-scale array circuits. Background technique [0002] In the display panel circuit design and integrated circuit design, limited by the semiconductor process, the circuit connection traces will form parasitic resistance, and the circuit signal current will have IRDrop (IR voltage drop, which refers to the presence in the integrated circuit) when it flows through the traces. A phenomenon in which the voltage drops or rises on the power and ground network) effect, this effect will make the voltage value of the key node of the circuit not meet expectations and is especially obvious in large-scale array circuits, so the array circuit needs to perform parasitic resistance DC The IRDrop effect simulation is used to obtain the precise voltage value actually...

Claims

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Application Information

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IPC IPC(8): G06F30/398
CPCG06F30/398
Inventor 童振霄刘伟平李相启魏洪川陆涛涛
Owner 成都华大九天科技有限公司
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